Design of low power 5-input majority voter in quantum-dot cellular automata with effective error resilience

Goswami, Mrinal; Sen, Bibhash; Sikdar, Biplab K.

doi:10.1109/ised.2016.7977063

Cited by 13 publications

(7 citation statements)

References 15 publications

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“…6 State-of-the-art Fault-tolerant five-input majority gates. (a) [31], (b) [22], (c) [32], (d) [24], (e) [26] Another design introduced in [31] is shown in Figure 6 (b). This cell is implemented with an efficient number of cells and has a smaller area compared to the design of [31].…”

Section: Fault-tolerant Five Input Majority Gatesmentioning

confidence: 99%

Design and energy analysis of a new fault-tolerant SRAM cell in quantum-dot cellular automata

2022

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Quantum-dot cellular automata (QCA) is an emerging technology proposed in response to the limitations of CMOS technology. Moreover, static RAM (SRAM) is a crucial part of memory design, and efficient RAM design can play a significant role in this regard. This paper proposes a fault-tolerant QCA SRAM cell based on QCA three-and five-input majority gates. A novel structure of QCA-RAM based on a fault-tolerant five-input majority cell is proposed, which outperformed its counterparts in terms of complexity, area, and total energy dissipation. The proposed design is implemented on a single layer and does not require any rotated cell, which significantly improves the manufacturability and robustness of the design. Furthermore, our design can tolerate a single omission fault. Our majority gate improves complexity, area, and energy dissipation, on average, by 54 %, 68 %, and 67 % in 1 Ek, respectively, as compared to its previous counterparts. The proposed fault-tolerant SRAM cell improves the complexity, area, and total energy dissipation by almost 13 %, 25 %, and 35 % in 1 Ek, respectively, as compared to its state-of-the-art QCA-based single-layer fault-tolerant counterpart.

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Section: Fault-tolerant Five Input Majority Gatesmentioning

confidence: 99%

Design and energy analysis of a new fault-tolerant SRAM cell in quantum-dot cellular automata

2022

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“…Moreover, three fault‐tolerant versions of the single‐layer full‐adder are also implemented by fault‐tolerant five‐input majority gates in previous works, illustrated in Figure A‐C.…”

Section: Proposed Fault‐tolerant Full‐addersmentioning

confidence: 99%

“…Three fault‐tolerant versions of the single‐layer full‐adder using fault‐tolerant five‐input majority gates in (A) Du et al, (B) Goswami et al, and (C) Sun et al [Colour figure can be viewed at wileyonlinelibrary.com]…”

Section: Proposed Fault‐tolerant Full‐addersmentioning

confidence: 99%

“…Table provides the stability results of outputs Sum and C out of the fault‐tolerant single‐layer full‐adders shown in Figure using the proposed fault‐tolerant five‐input majority gate and the fault‐tolerant five‐input majority gates in previous articles against single‐ and double‐cell omission defects.…”

Section: Proposed Fault‐tolerant Full‐addersmentioning

confidence: 99%

“…In another attempt to improve the tolerance of five‐input majority gate, Goswami et al have proposed a fault‐tolerant five‐input majority gate with a total of 27 cells at one clock. It has a tolerance of 28% and 100% at single‐cell and extra‐cell defects, respectively.…”

Section: Introductionmentioning

confidence: 99%

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Robust QCA full‐adders using an efficient fault‐tolerant five‐input majority gate

Ahmadpour

Mosleh

Heikalabad

2019

Circuit Theory & Apps

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Quantum-dot cellular automata (QCA) is considered as a top candidate for nanoscale technologies with unique features such as very low occupancy and ultralow power consumption. Despite the potential benefits of QCA technology over CMOS technology, QCA circuits are highly prone to defects. Therefore, a demand has risen in designing fault-tolerant circuits. In this research, a novel fault-tolerant five-input majority gate is first suggested, and then it is evaluated by implementing a variety of faults such as cell omission, cell displacement, and extra-cell deposition. The evaluation results reveal that the proposed structure is 100%, 51.85%, and 18.8% fault-tolerant under extra-cell deposition, single-cell omission, and double-cell omission, respectively. Moreover, two single-layer and coplanar fault-tolerant QCA full-adders are offered using the suggested fault-tolerant structure. The stability of the presented single-layer full-adder has also been investigated under single and double cell omission defects. The evaluation outcomes show that the suggested fault-tolerant single-layer full-adder has a high stability in Sum and C out outputs compared with other full-adders. In order to validate the functionality of the suggested fault-tolerant five-input majority gate, a number of physical investigations are given. The QCADesigner 2.0.3 software has been used to evaluate the simulation results.KEYWORDS five-input majority gate, circuit design, fault-tolerant, full-adders, nanotechnology, quantum-dot cellular automata (QCA)

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Designing Fault-Tolerant Digital Circuits in Quantum-Dot Cellular Automata

Marshal,

Raja Sekar,

Gopalakrishnan

et al. 2024

Design and Applications of Emerging Computer Systems

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Design of low power 5-input majority voter in quantum-dot cellular automata with effective error resilience

Cited by 13 publications

References 15 publications

Design and energy analysis of a new fault-tolerant SRAM cell in quantum-dot cellular automata

Design and energy analysis of a new fault-tolerant SRAM cell in quantum-dot cellular automata

Robust QCA full‐adders using an efficient fault‐tolerant five‐input majority gate

Designing Fault-Tolerant Digital Circuits in Quantum-Dot Cellular Automata

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