Design of low-offset constant transconductance rail-to-rail operational amplifier

Abstract

An operational amplifier based on UMC 40nm process is designed. PMOS and NMOS differential pairs are adopted in the input stage of the circuit to achieve rail-to-rail input, and the minimum current selection circuit is used to reduce the change rate of the transconductance of the input stage. The gain stage adopts a common source common gate structure. In order to obtain full swing output, class AB output stages are adopted, and the output MOS is biased by feedback technology. The CMRR of 85 . 1 4 dB and PSRR of 85 . 8 6 dB can be obtained. The open-loop gain is 90 dB, the phase margin is about 83°, the unit-gain bandwidth product is 15.84MHz, and the offset voltage is 283.9nV.