Design of low-error fixed-width modified booth multiplier

Cho, Kyung-Ju; Lee, Kwangchul; Chung, Jin-Gyun; Parhi, Keshab K.

doi:10.1109/tvlsi.2004.825853

Cited by 144 publications

(14 citation statements)

References 11 publications

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“…In this work, a novel binary to 2's complementing circuit and a 2-to-1 multiplexers are used to minimize the delay and power. Few fixed width Booth multiplier architectures have been suggested in [18][19][20][21][22] for optimization of area, delay, and power but at the cost of error in the output.…”

Section: Introductionmentioning

confidence: 99%

Area-delay eﬀicient Radix-4 8×8 Booth multiplier for DSP applications

Singhal¹,

Patel²,

Mahajan³

et al. 2021

Turk J Elec Eng & Comp Sci

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Booth multiplier is the key component in portable very large-scale integration (VSLI) systems enabled with signal and image processing applications. The area, delay, and energy are the major constraints in these systems. Therefore, in this paper, a detailed analysis of the state-of-the-art Booth multiplier architecture and its various internal units are presented to find the scope of optimization. Based on the finding of analysis, optimized new binary to 2's complement (B2C), Booth encoder-cum-selector type-1 and type-2, and partial product addition units are proposed. Furthermore, using these optimized units, an efficient parallel radix-4 8 × 8 Booth multiplier architecture is proposed.The simulation is carried out to verify the functionality of the proposed design. The synthesis results show that the proposed structure offers a saving of 13.56% in delay and 34.87% in area compared to the recent similar Booth multiplier design. Comparison results also reveal that the proposed Booth multiplier design involves 43.7% less area-delay-product and 11.24% less energy compared to the recent Booth multiplier design. Therefore, the proposed Booth multiplier design could be helpful for efficient realization of digital signal processing systems.

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Section: Introductionmentioning

confidence: 99%

Area-delay eﬀicient Radix-4 8×8 Booth multiplier for DSP applications

Singhal¹,

Patel²,

Mahajan³

et al. 2021

Turk J Elec Eng & Comp Sci

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“…Considering both operation accuracy and hardware complexity, several schemes based on truncation error compensation (TEC) have been presented for fixed-width Baugh-Wooley multipliers [5][6][7][8] or fixed-width Booth multipliers (FWBMs) [9][10][11][12][13][14][15][16][17][18][19][20][21][22]. The Booth multiplier has benefits in achieving high hardware efficiency because the number of rows of partial products is significantly reduced [23,24].…”

Section: Introductionmentioning

confidence: 99%

“…Therefore, the FWBM that enables a kind of TEC scheme is discussed in this study. A number of TEC schemes for FWBMs have been presented [9][10][11][12][13][14][15][16][17][18][19][20][21][22]. In general, TEC schemes for FWBMs obtain a TEC value (bias) based on computer simulation [9][10][11][12][13][14] or probability-based estimation [14][15][16][17][18][19][20][21][22] to compensate for the truncation error associated with the curtailed Electronics 2021, 10, 2511 2 of 19 partial products.…”

Section: Introductionmentioning

confidence: 99%

“…A number of TEC schemes for FWBMs have been presented [9][10][11][12][13][14][15][16][17][18][19][20][21][22]. In general, TEC schemes for FWBMs obtain a TEC value (bias) based on computer simulation [9][10][11][12][13][14] or probability-based estimation [14][15][16][17][18][19][20][21][22] to compensate for the truncation error associated with the curtailed Electronics 2021, 10, 2511 2 of 19 partial products. For simulation-based methods, the work in Reference [9] used linear regression analysis and simulation to generate bias values.…”

Section: Introductionmentioning

confidence: 99%

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An Accuracy-Improved Fixed-Width Booth Multiplier Enabling Bit-Width Adaptive Truncation Error Compensation

et al. 2021

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Fixed-width Booth multipliers (FWBMs) generate a product with the same bit width as the operand and have been extensively employed in many digital systems. Various truncation error compensation (TEC) schemes have been presented for FWBM designs, aiming to reduce hardware costs while preserving operation accuracy. In general, the existing TEC methods function adequately for an exact bit width of the operand but fail to consider the TEC effect for FWBM inputs with various bit-width levels. To address this issue, we propose a bit-width adaptive TEC (BWATEC) scheme for providing high-accuracy TEC functions that are adaptive to the multiple Lʹ-bit numerical ranges of input data for an L-bit FWBM (Lʹ ≤ L). We also present adjustable architecture for a 16-bit FWBM to enable the proposed BWATEC scheme and evaluate the hardware performance, using the TSMC 40 nm standard cell library. Relative to the contrast 16-bit FWBM approaches that use state-of-the-art TEC methods, the proposed BWATEC-enabled FWBM design can achieve reductions in the area-delay-error product of 7.9%–50.9%, 17.1%–69.5%, 29.9%–82.2%, and 100% for the 14-bit, 12-bit, 10-bit, and 8-bit inputs, respectively. Moreover, the resultant 16-bit FWBM with BWATEC was verified by using the field-programmable gate array for convolutional neural network acceleration.

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“…2 The proposed modulo ð2 n À 2 p þ 1Þ multipliers A booth multiplier is composed of a partial product generater, a CSA tree and a 2n À bit adder [6,7]. Based on booth multipliers, A½n À 1 : 0 Â B½n À 1 : 0 can be expressed as P½2n À 1 : 0 and N½2n À 1 : 0 , which are the outputs of a CSA Tree.…”

Section: Introductionmentioning

confidence: 99%