Design of Low-Complexity FIR Filters Based on Signed-Powers-of-Two Coefficients With Reusable Common Subexpressions

Abstract

Design of low-complexity FIR filters based on signed-powers-of-two coefficients with reusable common subexpressions

Double-Base Number System and Its Application in FIR Filter Design

“…The other category of algorithms is based on Common Subexpression Elimination (CSE), which has historically been adopted in computer-aided design in high-level synthesis and has now become a very popular dedicated approach to realizing VLSI efficient FIR filters in recent years [6,8,10,11,[24][25][26]. The main idea behind all these algorithms is the maximization of the sharing of common subexpressions, or the elimination of replicated subexpressions in the MCM block by pattern matching.…”

“…Due to the necessity to fix the positional notation in order to search for good common subexpressions, CSD [8,10,11,17,23,24,26] and MSD [34,35] representations have been widely adopted. As CSD is a unique representation while MSD may appear in more than one form for the same integer coefficient, CSD has the advantage of lower search complexity for common subexpressions but MSD is capable of producing better quality solution.…”

Optimization of Linear Phase FIR Filters in Dynamically Expanding Subexpression Space

“…First, the FIR filter is designed in a discrete space such as a finite wordlength space or SPT space to meet a given specification. In the second stage, a common subexpression elimination [1,7,8,18,20,23,24], a graph-based algorithm [2,3,10,21] or a difference algorithm [4,17,22] is applied on the discrete coefficients to find and share the common subexpressions. An obvious disadvantage of such a two-stage optimization is that the search space in the second stage is limited by the finite wordlength or SPT coefficients obtained in the first-stage optimization.…”

“…A local search algorithm is proposed in [24]. By constraining the search range and search patterns, the resulting filters have a tradeoff between the hardware cost and computational complexity.…”

“…The proposed algorithm generates filters using fewer adders than the algorithms proposed in [24,25,27]. The optimization time for problems with similar size varies heavily, but as an estimation the proposed algorithm can be used with length up to 50 and bit width up to 11 bits, and the solving time ranges from a few hours to a few tens of hours on a 3 GHz PC.…”