Design of linear ramp generator for ADC

Ashwini, S R; Sivakumar, M.; Rani, S. P. Joy Vasantha

doi:10.1109/icscn.2017.8085728

Cited by 5 publications

(4 citation statements)

References 4 publications

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“…As it can be seen, differences in the estimation of INL are well contained in the ±0.25 LSB band. It is interesting to notice that, as predicted by equation (10), the magnitude of the observed INL estimation error agrees very well with the step-wise nature of the generated ramp stimulus, which, for the selected ramp generator sample, has a step size of ∼ 0.2 LSB.…”

Section: B Static Linearity Measurements Using Step-wise Ramp Stimulisupporting

confidence: 72%

“…In essence, integrator-based ramp generators rely on a controlled current source that charges a capacitor in order to generate a ramp voltage signal [4]- [10]. The classic work in [4] presents a closed-loop ramp generator with a feedback circuitry that controls the slope of the generated ramp signal.…”

Section: Previous Workmentioning

confidence: 99%

“…Equations 6and (10) show that the described measurement strategy provides estimations of the DNL and INL metrics of an ADC, respectively, as a function of the discrete number of steps between two consecutive code transitions at the converter output, within the accuracy limits of the step size of the stepwise ramp stimulus used for exciting the ADC.…”

Section: B Measuring Adc Static Linearity Metrics Using Step-wise Ramentioning

confidence: 99%

“…Step-wise ramp generation 14.5 -2/2 0.06 65nm CMOS [4] Automatic slope adjustment ramp generation 8 -2/2 N/A N/A [5] Current source integration 14 * 0.1/0.9 0.11 2.0µm CMOS [5] Relaxation oscillator 12 * 0.2/1.4 0.51 1.2µm CMOS [6] Adaptive triangle-wave generation 14 * -1/1 0.05 0.6µm CMOS [9] Error-cancellation Least-Mean-Square integrator 10 N/A N/A N/A [9] SC fully-differential Least-Mean-Square integrator 11 0.7/1.3 0.18 180nm CMOS [17] Σ∆ modulation-based generation 12 * 0.4/1.4 0.02 250nm CMOS [8] Integration of voltage controlled current source 15 * 0/1 0.9 0.5µm CMOS [10] Bootstrap integrator-based generator > 8 * N/A N/A 180nm CMOS [15] Segmented resistor-string DAC 9 0/1.8 0.91 180nm CMOS * Electrical simulation results. with an average INL estimation error of 0.33 LSB, again in agreement with the expected error due to the discrete nature of the step-wise ramp stimulus.…”

Section: Referencementioning

confidence: 99%

See 3 more Smart Citations

Fully Differential 4-V Output Range 14.5-ENOB Stepwise Ramp Stimulus Generator for On-Chip Static Linearity Test of ADCs

Renaud

Diallo

Barragán

et al. 2019

IEEE Trans. VLSI Syst.

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This paper presents an on-chip step-wise ramp stimulus generator aimed at static linearity test applications for ADCs. The proposed ramp stimulus generator is based on a simple switched-capacitor integrator with a constant DC input. The integrator has been conveniently modified to produce a very small integration gain proportional to the capacitance difference of two capacitors, in such a way that the resulting step-wise ramp signal at the output has a step size below the LSB of the target ADC under test. In order to verify the feasibility of the proposed ramp generation technique, this paper details the design and experimental characterization of a proof-of-concept step-wise ramp generator in a 65 nm CMOS technology. Experimental results on 15 fabricated samples show an average linearity of 14.5 effective bits in a differential output range of ±2 V. Moreover, a discrete-time static linearity measurement strategy is proposed and, as a proof-of-concept validation, it is verified on an offthe-shelf 11-bit ADC using the fabricated generator samples. Experimental results show an accuracy of ±0.3 LSB in the measurement of the INL of the ADC under test.

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Section: B Static Linearity Measurements Using Step-wise Ramp Stimulisupporting

confidence: 72%