Design of integrated 1.6 GHz, 2 W tuned RF power amplifier

Abstract

This paper describes the design of an integrated tuned power amplifier specified to operate at Inmarsat satellite uplink frequencies from 1626.5 to 1660.5 MHz. The basic topology of the amplifier lies on the parallel tuned inverse class E amplifier that is modified by placing the DC-blocking capacitor into a new position and by adjusting the size of the capacitor to improve stability below the desired band. Further, the new positioning reduces losses between drain and load. The high currents flowing in the circuit made it necessary to use wide inductor width and high-Q finger capacitors in the on-chip resonator. The amplifier was implemented as a Gallium Arsenide (GaAs) integrated circuit (IC) that delivered 2 W of output power while the drain efficiency was ca. 56%. Measurements included source and load pulls to further improve the performance of the amplifier and to investigate the stability at small input drive levels.

Dimensioning space of a parallel tuned amplifier

“…Compared with measurement results from [7] neither the simulations done in that work nor the approach here can explain the initially measured low output power, about 0.9 W achieved without any further tuning to the implemented amplifier. However, the procedure here seems to match relatively well with simulations done with the implemented amplifier using foundry components.…”

“…The S-parameters from the EM-simulated resonator were used to derive a discrete resonator with five additional parasitics shown in Fig. 4 When we compare the simulation results from the amplifier designed in [7], output power was about 3.4 W and efficiency around 70 %. If we approximate the value of the parameter from EM simulations and of the transistor from the loadlines (assuming that the output capacitance is linear), we get roughly -0.286 and 0.1447, respectively.…”

“…6, which shows the simulated loadlines of three transistors located at the very ends and in the center of a tuned amplifier. This transistor is used and implemented in [7]. The loadlines are obtained by taking the simulated drain current and subtracting a proper 1 term which eliminates any negative swings of both drain current and dissipated power.…”

“…The circuit topology in this paper is related to the implemented amplifier in [7], where a modification to inverse class E topology was done by setting the DCblock capacitor into a different place and by the removal of series inductive component between the transistor and the resonator at the output. The analysis of this topology together with transistor output capacitance, bias inductance and both with and without the effects of matching is inspired by the work of M. Kazimierczuk [6].…”