Design of Higher Order Matched FIR Filter Using Odd and Even Phase Process

Abstract

The current research paper discusses the implementation of higher order-matched filter design using odd and even phase processes for efficient area and time delay reduction. Matched filters are widely used tools in the recognition of specified task. When higher order taps are implemented upon the transposed form of matched filters, it can enhance the image recognition application and its performance in terms of identification and accuracy. The proposed method i.e., odd and even phases' process of FIR filter can reduce the number of multipliers and adders, used in existing system. The main advantage of using higher order tap-matched filter is that it can reduce the area required, owing to its odd and even processes. Further, it also successfully reduces the time delay, especially in case of high order demands. The performance of higher order matched filter design, using odd and even phase process, was analyzed using Xilinx 9.1 ISE Simulator. The study results accomplished reduction in area, 70% increase in throughput compared to traditional implementation and reduced time delay. In addition to these, Vedic multiplier-based FIR is modified with a tree-based MAM that reduces the number of shifter and adder to replace the multiplier.

Design of Modified RNS-PPA Based FIR Filter for High-Speed Application

“…Whereas multiplication operation annihilates the performance time in most DSP application algorithms, hence we need to choose the highspeed multiplier. presently, multiplication execution time was the most annihilating factor while determining the instruction cycle [3] time of a DSP chip. The enormous expansion of digital system applications and computers causes the demand for the development of high-speed processing systems.…”

“…Dynamic range is the multiplication of all primes set by moduli. And often it can be denoted by M, the mathematical form is shown in (3).…”