Design of high speed MOS multiplier and divider using redundant binary representation

Kuninobu, Shigeo; Nishiyama, T.; Edamatsu, H.; Taniguchi, Takashi; Takagi, Naofumi

doi:10.1109/arith.1987.6158706

Cited by 129 publications

(68 citation statements)

References 4 publications

(5 reference statements)

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“…al. [5] have proposed some of the most efficient designs for a cell that adds radix-2 signed-digit operands. We have therefore adopted the same design methodology.…”

Section: Static Cmos Implementationmentioning

confidence: 99%

“…The carries c i 2 and c i 1 can take values in 1 0 1 and need two bits for encoding. Following [5] we encode each of these carries using two unipolar binary variables, each requiring a single bit.…”

Section: Static Cmos Implementationmentioning

confidence: 99%

“…Signed-digit adder trees are easier to lay out and route than Wallace trees. In [5] a 64 ¢64 bit multiplier based on a redundant signed-digit binary adder tree was shown to yield a smaller critical path delay than the corresponding Wallace tree multiplier. A similar design for a fast 54 ¢54 bit multiplier was recently presented in [6].…”

Section: Introductionmentioning

confidence: 99%

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Hybrid signed-digit number systems: a unified framework for redundant number representations with bounded carry propagation chains

Phatak

Koren

1994

IEEE Trans. Comput.

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A novel hybrid number representation is proposed in this paper. It includes the two's complement representation and the signed-digit representation as special cases. The hybrid number representations proposed are capable of bounding the maximum length of carry propagation chains during addition to any desired value between 1 and the entire word length. The framework reveals a continuum of number representations between the two extremes of two's complement and signed-digit number systems and allows a unified performance analysis of the entire spectrum of implementations of adders, multipliers and alike.We present several static CMOS implementations of a two-operand adder which employ the proposed representations. We then derive quantitative estimates of area (in terms of the required number of transistors) and the maximum carry propagation delay for such an adder. The analysis clearly illustrates the tradeoffs between area and execution time associated with each of the possible representations. We also discuss adder trees for parallel multipliers and show that the proposed representations lead to compact adder trees with fast execution times.In practice, the area available to a designer is often limited. In such cases, the designer can select the particular hybrid representation that yields the most suitable implementation (fastest, lowest power consumption, etc.) while satisfying the area constraint. Similarly, if the worst case delay is predetermined, the designer can select a hybrid representation that minimizes area or power under the delay constraint.

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“…al. [5] have proposed some of the most efficient designs for a cell that adds radix-2 signed-digit operands. We have therefore adopted the same design methodology.…”

Section: Static Cmos Implementationmentioning

confidence: 99%

Section: Static Cmos Implementationmentioning

confidence: 99%

See 1 more Smart Citation

Hybrid signed-digit number systems: a unified framework for redundant number representations with bounded carry propagation chains

Phatak

Koren

1994

IEEE Trans. Comput.

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“…F. Conversion from RB to NB: Though it is advantages to deal with RB addition, we deal with only the NB number system in the real world. Hence the output obtained in RB form has to be converted into the NB form [7,8]. This conversion is performed first by encoding the NB numbers to RB form separating the X+ and X-parts as given in table I. X+ is the positive digit of X and X-is the negative digit of X.…”

Section: Redundant Binary Number Systemmentioning

confidence: 99%

An Efficient CircularConvolution using Higher Radix-256 Booth Encoding Algorithm

2018

IJRTER

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-Convolution algorithm play a key role in digital processing applications. They involve many multiplication steps and consume a lot of processing time. As such, they play a vital role in determining the performance of the digital signal processor. Convolution implemented with Vedic mathematics proved fast as compared to those using conventional methods of multiplication and division. This paper presents a novel VerilogHDL implementation of convolution algorithm with multiplier using radix-256 booth encoding to reduce the partial product rows by eight fold and carry propagate free redundant binary addition for adding the partial products, thus, contributing to higher speed. The entire design was implemented in Xilinx ISE 13.1 targeted towards Virex-7.

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“…For instance, the same Signed Digit adder (from [8]) and the same shifter, were used (supplied as structural Verilog modules). Likewise the same ROM was used in all methods.…”

Section: Methodsmentioning

confidence: 99%

Comparison of branching CORDIC implementations

Singh

Phatak

Goff

et al.

Proceedings IEEE International Conference on Application-Specific Systems, Architectures, and Processors. ASAP 2003

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In this paper we compare implementations of Duprat and Muller's Branching CORDIC and Phatak's DoubleStep Branching (DSB)-CORDIC algorithms for Sine and Cosine evaluation. For reference we also report on classical CORDIC implementations for the same wordlengths. We have also implemented Double Stepping in the classical algorithm and report on the performance of this method.CORDIC evaluation of Sine and Cosine includes two parts, the Zeroer and the Rotator. We discuss implementation issues related to the minimization of the delay of each iteration of the algorithm (including delays for both the Zeroer as well the Rotator). We then examine hybrid methods that select the components from different algorithms (such as a DSB Zeroer together with a classical rotator or vice versa).

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Design of high speed MOS multiplier and divider using redundant binary representation

Cited by 129 publications

References 4 publications

Hybrid signed-digit number systems: a unified framework for redundant number representations with bounded carry propagation chains

Hybrid signed-digit number systems: a unified framework for redundant number representations with bounded carry propagation chains

An Efficient CircularConvolution using Higher Radix-256 Booth Encoding Algorithm

Comparison of branching CORDIC implementations

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