Design of high-performance 32-bit embedded processor

Kim, Jihoon; You, Duk-Hyun; Kwon, Kiseok; Bae, Eunjoo; Son, WonHee; Park, In-Cheol

doi:10.1109/socdc.2008.4815746

Cited by 2 publications

(4 citation statements)

References 3 publications

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“…Secondly comparison is done with Leon2 core on the basis of area and power consumption, then comparison of implementation is done among various Xilinx devices for power and speed which is shown in table II. Another comparison of among different processor core [1] in fig.7 with embedded RISC is done on the basis of power used, operating speed and process technology used, which shows appreciable improvement.…”

Section: Simulation and Synthesis Resultsmentioning

confidence: 99%

Implementation of embedded RISC processor with dynamic power management for low-power embedded system on SOC

Kumar

Rattan

2015

2015 2nd International Conference on Recent Advances in Engineering &Amp; Computational Sciences (RAECS)

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The SOCs produced nowadays provide a high level of functionality, serve a wide range of applications, while becoming more efficient and cost effective. The complexity of the SOCs is also reaching its peak level. Around 10 to 12 numbers of analog IPs and digital IPs blocks are incorporated into the single SOC. It also supports multiple voltage domains that often simultaneously a combination of internal and external regulation modes. For modern age embedded systems to operate with high range of power and performance, the system must be power aware but not just consume low power. This paper presents the design detail of embedded RISC processor with dynamic power management capability. In this paper, we implemented a RISC processor with power management that keeps on tracking access to I/O devices while processing and power aware techniques within coding that lower the power consumption of system. Paper describes about the proposed system architecture, synthesis and simulation results analysis of the design. The coding is done with verilog-HDL and these coded designs are synthesized and simulated using Xilinx ISE 12.3 (Xilinx ISim simulator) and power calculation is done using Xilinx Xpower analyzer. Keywords-Dynamic voltage scaling (DVS), Dynamic frequency scheduling (DFS), hardware description language (HDL), Reduced Instruction set computer (RISC), system-on-chip (SoC), field programmable gate array (FPGA).

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Section: Simulation and Synthesis Resultsmentioning

confidence: 99%

Implementation of embedded RISC processor with dynamic power management for low-power embedded system on SOC

Kumar

Rattan

2015

2015 2nd International Conference on Recent Advances in Engineering &Amp; Computational Sciences (RAECS)

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“…For a MIPS processor, the average amount of NOP instructions is about 10% [5]. Also, many RISC designs include a branch delay slot, a position after a branch instruction that can be filled with an instruction that is executed regardless of whether the branch is taken or not.…”

Section: Core-a Instruction Set Architecturementioning

confidence: 99%

“…Additionally, Core-A is designed to easily support IP-level clock gating for lowpower consumption. Its five-stage implementation can run at 260MHz and requires just 32K logic gates when fabricated in a 180nm CMOS process [5]. It occupies only 0.47mm 2 and its power efficiency is about 0.35mW/MHz.…”

Section: Core-a Hardware Implementationmentioning

confidence: 99%

“…It has a unique instruction set architecture, and the development environment is well established by porting the GNU Compiler Collection (GCC) and by including an on-chip hardware debugger. Its five-stage implementation can run at more than 200MHz and requires just 32K logic gates when fabricated in 130nm and 180nm complementary metal-oxide semiconductor (CMOS) processes [5]. It was designed using Verilog-HDL, and the source code is in the public domain and available without royalty.…”

Section: Introductionmentioning

confidence: 99%

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Core-A: A 32-bit Synthesizable Processor Core

Kim¹,

Lee²,

Ando³

2015

IEIE Transactions on Smart Processing and Computing

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Core-A is 32-bit synthesizable processor core with a unique instruction set architecture (ISA). In this paper, the Core-A ISA is introduced with discussion of useful features and the development environment, including the software tool chain and hardware on-chip debugger. Core-A is described using Verilog-HDL and can be customized for a given application and synthesized for an application-specific integrated circuit or field-programmable gate array target. Also, the GNU Compiler Collection has been ported to support Core-A, and various predesigned platforms are well equipped with the established design flow to speed up the hardware/software co-design for a Core-A-based system.

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Design of high-performance 32-bit embedded processor

Cited by 2 publications

References 3 publications

Implementation of embedded RISC processor with dynamic power management for low-power embedded system on SOC

Implementation of embedded RISC processor with dynamic power management for low-power embedded system on SOC

Core-A: A 32-bit Synthesizable Processor Core

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