Design of High-Order Switches for Multimode Applications on a Silicon-on-Insulator Technology

Tombak, A.; Carroll, Michael S.; Kerr, D.; Pierres, Jean-Blaise; Spears, E.

doi:10.1109/tmtt.2013.2277989

Cited by 37 publications

(17 citation statements)

References 17 publications

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“…The world leading RF device vendor Skyworks investigated a novel SP5T module for WLAN application in 2013 [1], RFMD demonstrated a SP6T featuring P-0. and SP10T with adequate intermodulation and harmonic distortion performance in 2010 [3] and this July [4], respectively. To the best of authors' knowledge, the highest throw count antenna switch implemented in SOI technology by now is 14 which is reported by Anadigics [5], whose P-0.1 dB is 28 dBm for all cellular bands.…”

Section: Introductionmentioning

confidence: 96%

Monolithic Single-Pole Sixteen-Throw T/R Switch for Next-Generation Front-End Module

Cui

Chen

Liu

2014

IEEE Microw. Wireless Compon. Lett.

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A broadband monolithic linear single-pole, sixteenthrow (SP16T) antenna switch has been designed and fabricated in 180 nm thin film SOI CMOS process, which is intended for the next generation multimode multiband (MMMB) cellular applications. The switch features the minimum 0.7 dB and average 1dB insertion loss, 0.1 dB compression point of 29 dBm and at least 33 dB isolation at all cellular bands for mobile front ends by applying distributed architecture and adaptive supply voltage generator. To the best of our knowledge, this work is the first demonstration of SP16T antenna switch with superior isolation and power handling capacities for most of the known cellular bands with satisfactory harmonic and intermodulation distortion performance on SOI. The simulated and measured results show excellent agreement.Index Terms-Multimode multiband (MMMB), silicon-on-insulator (SOI), switches.

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Section: Introductionmentioning

confidence: 96%

Monolithic Single-Pole Sixteen-Throw T/R Switch for Next-Generation Front-End Module

Cui

Chen

Liu

2014

IEEE Microw. Wireless Compon. Lett.

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“…This increases the complexity of the hardware. In [7], the measured spurious levels were typically better than 120 dBm and 97 dBm on a 100-kHz resolution bandwidth in Rx and Tx modes, respectively. In [15], it was reported that the measured spurious levels were typically better than 110 and 91 dBm in Rx and Tx modes.…”

Section: New Biasing Strategy Without Negative Bias Voltagementioning

confidence: 97%

“…Several state-of-the-art techniques such as a floating gate or body method [4], a negative biasing method [5], and a stacked-FET technique [6] have been devised in order to handle a high power signal to 40 dBm under the worst case for antenna impedance mismatch, and therefore recently published SOI CMOS antenna switches adopting these techniques have shown excellent power-handling capability and harmonic distortion performance with small IL [7]- [9]. Nevertheless, there are still some problems to overcome.…”

mentioning

confidence: 99%

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A Stacked-FET Linear SOI CMOS Cellular Antenna Switch With an Extremely Low-Power Biasing Strategy

Kim

et al. 2015

IEEE Trans. Microwave Theory Techn.

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A stacked field-effect transistor (FET) linear cellular antenna switch adopting a transistor layout with odd-symmetrical drain-source metal wiring and an extremely low-power biasing strategy has been implemented in silicon-on-insulator CMOS technology. A multi-fingered switch-FET device with odd-symmetrical drain-source metal wiring is adopted herein to improve the insertion loss (IL) and isolation of the antenna switch by minimizing the product of the on-resistance and off-capacitance. To remove the spurious emission and digital switching noise problems from the antenna switch driver circuits, an extremely low-power biasing scheme driven by only positive bias voltage has been devised. The proposed antenna switch that employs the new biasing scheme shows almost the same power-handling capability and harmonic distortion as a conventional version based on a negative biasing scheme, while greatly reducing long start-up time and wasteful active current consumption in a stand-by mode of the conventional antenna switch driver circuits. The implemented single-pole four-throw antenna switch is perfectly capable of handling a high power signal up to 35 dBm with suitably low IL of less than 1 dB, and shows second-and third-order harmonic distortion of less than 45 dBm when a 1-GHz RF signal with a power of 35 dBm and a 2-GHz RF signal with a power of 33 dBm are applied. The proposed antenna switch consumes almost no static power.Index Terms-Antenna switch, cellular, negative voltage, powerhandling capability, power loss, silicon-on-insulator (SOI), stacked field-effect transistor (FET), switch driver, switch-FET device.

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“…Generally, SOI-CMOS switches integrate a positive-voltage generator (PVG) and negative-voltage generator (NVG) on chip for the bias of the switch-FETs [8,9,10,11,12]. A charge pump to generate the negative voltage is extremely imperative in the antenna switch module and GSM-based switch applications result from the string requirements of power handling and harmonics distortion.…”

Section: Introductionmentioning

confidence: 99%

Dual SPDT/SP3T SOI CMOS switch adopting alternative bias strategy with enhanced performance compared to the conventional case

Zhang

et al. 2016

IEICE Electron. Express

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A dual single-pole double-throw (SPDT)/single-pole three throw (SP3T) distribution switch without the employment of negative voltage generator (NVG) for multi-mode multi-band applications has been designed and fabricated in a 0.18 µm silicon-on-insulator (SOI) CMOS process. To reduce power dissipation and prevent the noise from affecting the RF signal, an alternative bias strategy driven only by the positive voltage generator (PVG) is presented. Besides, LC impedance matching network are designed in both series and shunt branch to improve the insertion loss (IL) and isolation, respectively. For comparing the potential performance distinction, a switch version with conventional negative bias method is also implemented, which shows an IL of 0.41/0.65 dB and minimum isolation of 26.9/23.6 dB at 0.9/1.9 GHz, respectively. The presented switch adopting alternative bias scheme achieves improved IL of 0.37/0.53 dB and minimum isolation of 24.2/32.5 dB at 0.9/1.9 GHz, respectively. Both cases reveal comparative power handling capability and harmonic performance, while the active current consumption in the stand-by mode is significantly reduced with the new bias strategy.

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Design of High-Order Switches for Multimode Applications on a Silicon-on-Insulator Technology

Cited by 37 publications

References 17 publications

Monolithic Single-Pole Sixteen-Throw T/R Switch for Next-Generation Front-End Module

Monolithic Single-Pole Sixteen-Throw T/R Switch for Next-Generation Front-End Module

A Stacked-FET Linear SOI CMOS Cellular Antenna Switch With an Extremely Low-Power Biasing Strategy

Dual SPDT/SP3T SOI CMOS switch adopting alternative bias strategy with enhanced performance compared to the conventional case

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