Design of High-IF Discrete-Time Receivers for IoT: Demystifying Aliasing Trade-Offs

Abstract

Discrete-time (DT) receiver (RX) architectures offer low-power implementation, high configurability, and easy portability to ever finer CMOS nodes. Such features are highly desirable in IoT applications. To fully explore their advantages, a deep understanding of aliasing impairments that they entail is critical. However, such a discussion has not been sufficiently explored in the literature. In this tutorial brief, we start with a DT filter, which is at the core of a DT-RX. Next, a highintermediate-frequency (IF) architecture is chosen to demonstrate how aliasing is an intrinsic part of a DT-RX and how it affects key system design aspects. Further on, we discuss the application of decimation techniques and the stringent trade-offs involved.

Discrete-time Receivers, from N-Path to Charge Sharing Band-pass Filters: a Comparison

“…Complex band-pass filters (BPF) can also be implemented using the CS signal processing, enabling the development of intermediate frequency (IF) super-heterodyne receivers [26,50,54,55]. In Fig.…”

“…BPF center frequency (f c ) is easily programmed by changing the ratio between C H and C R for a specific f s according to (9), as shown in [27,54]…”