Design of heterogeneous MPSoC on FPGA

Zhang, Wenting; Geng, Lei; Zhang, Duoli; Du, Guotong; Gao, Minglun; Zhang, Wei; Hou, Ning; Yi-hua, Tang

doi:10.1109/icasic.2007.4415577

Cited by 13 publications

(3 citation statements)

References 2 publications

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“…Figure 10 presents the Virtex-7 FPGA resource utilization based on different projects [32]- [37], including the HW_nMPRA_RTOS project (4 instPi soft-core only) with a dynamic hardware scheduler. Table VI shows the overhead results related to RTOS functions and services partially or fully implemented in hardware by the nHSE scheduler and other CPU architectures.…”

Section: Comparison Between Different Cpu Architectures Based On Fpga...mentioning

confidence: 99%

“…[29], [33], [34, [35, [36], [37], architectures with the most produced ISAs such as ARM [30], or specific architectures of FPGA circuit manufacturers such as MicroBlaze [31], NIOS [32]. In the specialized literature, numerous highly established studies are proposed that implement some features of RTOS in hardware and that are designed for time-predictable systems, such as MERASA [40], PRET [41] and Patmos [22], [42].…”

Section: Comparison Between Different Cpu Architectures Based On Fpga...mentioning

confidence: 99%

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Custom Soft-Core RISC Processor Validation Based on Real-Time Event Handling Scheduler FPGA Implementation

Zagan

Găitan

2023

IEEE Access

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In dynamic real-time systems (RTS), the synchronous communication model is a source of unpredictable behaviors caused by the difficulty of estimating the maximum lockdown time in a process. Inter-task communication is a critical issue in RTS, even in the case of uniprocessor architectures. Using an FPGA-based development platform, through an SoC project, the implementation of HW_nMPRA_RTOS (a unified acronym for multi pipeline register architecture (nMPRA) where n is the degree of datapath resource multiplication, hardware scheduler engine (nHSE) for n threads and RTOS application programming interface (API)), dedicated processor architecture was developed, simulated and validated. This paper propose an innovative soft-core implementation to reduce interrupt latencies, while maintaining strong spatial and temporal isolation. Among the results which contain relevance and novelty, we can mention: rapid tasks context switching (1 clock cycle); The implementation of a distributed and versatile interrupt system which allows the interrupt attachment to any task; The implementation of a static scheduler and support for the dynamic tasks scheduling; Rapid response to events of up to 2 clock cycles. We demonstrate the architecture's predictability, scalability, and performance by running a set of benchmark applications on several configurations of HW_nMPRA_RTOS synthesized on a Xilinx 7 Series FPGA.INDEX TERMS Hardware RTOS, microprocessor, scheduling, field-programmable gate arrays (FPGA), real-time systems

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Section: Comparison Between Different Cpu Architectures Based On Fpga...mentioning

confidence: 99%

Section: Comparison Between Different Cpu Architectures Based On Fpga...mentioning

confidence: 99%

Custom Soft-Core RISC Processor Validation Based on Real-Time Event Handling Scheduler FPGA Implementation

Zagan

Găitan

2023

IEEE Access

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“…The type of propulsion for electric vehicles adopts three main engine configurations: hybrid electric vehicle (HEV), plugged hybrid electric vehicle (PHEV), and fully electric vehicle (FEV) [13][14][15], with the only difference in the autonomy, regarding the battery, which is maximum for the FEV and minimum for the HEV, with an intermediate value for the PHEV, closer to HEV than to EV. In present days, there is a large variety of lithium batteries for electric vehicles with different configurations and structures depending on the type and composition of electrodes and electrolytes that tend to provide the best performance possible [16][17][18][19][20][21][22][23][24]; therefore, it is very complicated to characterize the performance of all lithium batteries. Besides, the performance of a battery depends on the discharge rate and time of use, which makes it more difficult to predict the behavior of the battery.…”

Section: Introductionmentioning

confidence: 99%

Simulation of the Performance of Li-Ion Batteries in DC/AC Operating Mode for Electric Vehicles

Armenta-Deu,

Carriquiry

2024

Preprint

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This work simulates the performance of lithium batteries for electric vehicles under different charge and discharge rates. The simulation is based on similarity factors for power, voltage and current, reproducing the real operation conditions of an electric vehicle at the model scale. Most current driving modes have been analysed corresponding to discharge rates from 0.1C to 0.37C. The simulation has also been applied to determine charging time using charge power in real conditions, from 6.1 kW to 18.3 kW (0.1 C to 0.3C). Driving conditions are obtained using equations for vehicle motion including all forces. Tests have been run under two configurations, continuous and alternate current circuits, to reproduce the two types of engines that electric vehicles use. The simulation shows very good agreement in charge and discharge processes, average deviation of 3% related to real conditions, and 1.6% between them, which proves the validity of the simulation process.

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FPGA implementation of hardware accelerated RTOS based on real-time event handling

Zagan

Găitan

2023

J Supercomput

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Actual trends in the real-time system field consists of migration towards complex central processing unit (CPU) architectures with enhanced execution predictability and rapid CPU contexts switch, thus obtaining high-performant control systems. The main objective of this paper is to present the results obtained following the implementation of real-time operating systems (RTOS) functions in hardware. Based on the CPU resource multiplication concept, actual researches has been focused on synthesizing in field-programmable gate array (FPGA) and implementing innovative solutions to improve RTOS performance. The results are materialized by validating an efficient hardware scheduler micro-architecture, from which a remarkable efficiency and a plus of performance and predictability are obtained. The experimental results, the FPGA resource requirements for implementation of the processor in different configurations, and the comparisons with other similar processor architectures are presented in order to verify theoretical aspects proposed through this paper.

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Design of heterogeneous MPSoC on FPGA

Cited by 13 publications

References 2 publications

Custom Soft-Core RISC Processor Validation Based on Real-Time Event Handling Scheduler FPGA Implementation

Custom Soft-Core RISC Processor Validation Based on Real-Time Event Handling Scheduler FPGA Implementation

Simulation of the Performance of Li-Ion Batteries in DC/AC Operating Mode for Electric Vehicles

FPGA implementation of hardware accelerated RTOS based on real-time event handling

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