Design of Fast-Locked Digitally Controlled Low-Dropout Regulator for Ultra-low Voltage Input

Yang, Wei-Bin; Lin, Yi‐Chen; Lo, Yu-Lung

doi:10.1007/s00034-017-0642-2

Cited by 4 publications

(4 citation statements)

References 23 publications

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“…Adjust Frequency Adjust Frequency Hybrid A/D Converter BAWP, 3D power stage JSSC'17 [18] CICC'15 [17] BAWP, 2D power stage JSSC'13 [16] BAWP Digital LDO ESSCIRC'18 [19] Hybrid, Coarse-Fine-Tuning IET Circuit'13 [20] GVCO, Counter A-SSCC'11 [22] Shift Register ISSCC'17 [24] ADC, ED control PI control ICIIECS'15 [29] Shift register, DET, Coarse-Fine-Tuning KBEI'17 [28] Counter, Decoder, Coarse-Fine-Tuning Shift Register IEICE'11 [15] JSSC'17 [23] Coarse-Fine-Tuning, CMF ADC MEJ'12 [21] VCDL, Counter CSSP'17 [11] VCDL, Counter, Fast lock TSCII'16 [25] Shift register, Coarse-Fine-Tuning, Burst-Mode NEWCAS'16 [27] Shift Register, Coarse-Fine-Tuning, Freq hop ISSCC '18[35] Hybrid, Analog-Assist JSSC '18[36] Hybrid, Analog-Assist ISCAS'18 [33] Hybrid, Coarse-Fine-Tuning A-SSCC'16 [26] Dual loop(Analog+ Digitgal) IEEE Access'20 [30] Dynamic Frequency Scaling IEEE Trans. Power Electron.…”

Section: Thermometer Code Binarymentioning

confidence: 99%

“…1, the system-on-a-chip (SoC) of a wearable electronic product includes various analog, digital, mixed-signal, and RF circuits. In references [1]- [11], many circuits with a supply voltage of 0.3V have been proposed. Therefore, the design of power management IC will focus on ultra-low voltage design to achieve ultra-low power consumption.…”

Section: Introductionmentioning

confidence: 99%

“…The circuit architecture is divided into three parts: synchronous, asynchronous and hybrid. Most architectures of digital LDOs are synchronous system [11][20]- [25][27]- [32]. The advantage of the synchronous digital LDO is that the design is simple, and the clock is responsible for the operation of the circuit.…”

Section: Introductionmentioning

confidence: 99%

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Asynchronous Digital Low-Dropout Regulator With Dual Adjustment Mode in Ultra-Low Voltage Input

Yang¹,

Sun

Roy

et al. 2021

IEEE Access

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This paper presents the asynchronous digital low-dropout regulator (AD-LDO) with dual adjustment mode in ultra-low voltage input. The architecture of the proposed AD-LDO consists of the asynchronous control loop and the power PMOS array. The proposed AD-LDO is controlled by switched bidirectional asynchronous control loop which can eliminate the clock power consumption of synchronous LDO. The dual adjustment mode can not only provide wider loading current, but also can reduce output voltage ripple. Moreover, the proposed AD-LDO only uses one bidirectional asynchronous control loop for two adjustment modes, so it can save area and reduce power consumption. Under the 350mV input voltage and 300mV output voltage, the proposed AD-LDO can provide 2.4mA output current with 99.8% current efficiency and only consume 5μA quiescent current. Therefore, the proposed LDO is suitable for applications of wearable electronic devices with an ultra-low supply voltage.INDEX TERMS Asynchronous digital low-dropout regulator, asynchronous control loop, ultra-low voltage, dual adjustment mode, wearable electronic devices.

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Section: Thermometer Code Binarymentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Asynchronous Digital Low-Dropout Regulator With Dual Adjustment Mode in Ultra-Low Voltage Input

Yang¹,

Sun

Roy

et al. 2021

IEEE Access

Self Cite

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show abstract

“…Internet of Things (IoT), mobile and medical application have urge the Very Large Scale Integrated circuites (VLSI) designer to build ultra-low power (ULP) circuits [1,2]. Since power consumption deceases quadratically with the drop of supply voltage, low-voltage technology is one of the important means to reduce the power consumption of digital circuits [3][4][5]. As power supply voltages are scaling down to near/sub-threshold, traditional power management faces new challenges [6,7].…”

Section: Introductionmentioning

confidence: 99%

A Fast-Transient All-Digital LDO with Adaptive Clock Technique

Jia

Qiao

et al. 2019

Electronics

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To get a better tradeoff between the transient performance and current efficiency of Digital Low-Dropout (DLDO) regulator, this paper proposes an all-digital Low-Dropout (LDO) regulator with adaptive clock technique. The sample clock is supplied by a proposed digital oscillator (DOSC) whose output frequency can be changed seamlessly. The frequency of sample clock and loop gain boost adaptively when the output voltage undershoot/overshoot is detected. Proposed DLDO integrates a ripple controller to eliminate steady-state supply ripple and reduce steady-state power. The proposed DLDO is simulated at Semiconductor Manufacturing International Corporation (SMIC) 55 nm with 5.03e-4 mm2 active area. The simulation results show that the operating voltage of proposed DLDO can be down to 0.5 V and the peak current efficiency is 99.99%. The measured voltage undershoot is 40 mV and transient response time is 500 ns with load step of 10 to 800 uA.

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A Low-Power High-Gain Low-Dropout Regulator for Implantable Biomedical Applications

Boanloo

Yavari

2020

Circuits Syst Signal Process

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Design of Fast-Locked Digitally Controlled Low-Dropout Regulator for Ultra-low Voltage Input

Cited by 4 publications

References 23 publications

Asynchronous Digital Low-Dropout Regulator With Dual Adjustment Mode in Ultra-Low Voltage Input

Asynchronous Digital Low-Dropout Regulator With Dual Adjustment Mode in Ultra-Low Voltage Input

A Fast-Transient All-Digital LDO with Adaptive Clock Technique

A Low-Power High-Gain Low-Dropout Regulator for Implantable Biomedical Applications

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