Design of Efficient Reversible Fault tolerant Adder/Subtractor

Abstract

In recent years, reversible logic is the most popular and emerging technology and it will be having wide applications in the field of Low power CMOS, quantum computing and optical computing. Circuits with reversible logic gates provide low power dissipation and low energy loss. This paper proposes the Adder/Subtractor designs that are used in many DSP applications. This paper proposes the efficient Adder/Subtractor design in terms of gate count, garbage outputs, constant inputs and quantum cost. The proposed circuits will simulated using ModelSim simulator and implemented on Xilinx FPGA platform.