Design of double edge-triggered flip-flop for low-power educational environment

Abstract

Power consumption plays a significant role in any integrated circuit. In this study, an explicit type pulse trigger flip-flop is implemented using the CMOS 90 nm technology. For low-power dissipation, 1 V supply will optimize the size of gate terminal. This explicit type flip-flop uses an explicit source for pulse generation, that is, the double edge-triggered pulse generator, which requires half of clock frequency compared to the single edge-triggered pulse generator. The proposed new double edge-triggered pulse generator uses the pulse generation logic, which is used to share many numbers of flip-flop results at low power. In this article, circuits with low power, low heat generation, and increased durability are achieved.