1967
DOI: 10.1007/978-3-662-38101-4
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Design of Digital Computers

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Cited by 31 publications
(5 citation statements)
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“…In other words, equivalent-circuit constructions can help to gain a deeper understanding of nanocomputing circuits, which operate on different principles than today's electronic devices. One can view field-coupled nanomagnets as a nanoscale reintroduction of the ferrite-ring magnetic computers [10][11][12], where the electric interconnection circuits (coils, rectifiers, etc.) are substituted by the magnetic stray field of the magnets.…”
Section: Discussionmentioning
confidence: 99%
See 1 more Smart Citation
“…In other words, equivalent-circuit constructions can help to gain a deeper understanding of nanocomputing circuits, which operate on different principles than today's electronic devices. One can view field-coupled nanomagnets as a nanoscale reintroduction of the ferrite-ring magnetic computers [10][11][12], where the electric interconnection circuits (coils, rectifiers, etc.) are substituted by the magnetic stray field of the magnets.…”
Section: Discussionmentioning
confidence: 99%
“…On the macroscale, magnetic amplifiers [8,9] and ferrite-ring logic devices [10][11][12] operate by processing and propagating signals via the magnetic fields of ferromagnetic cores. Spin waves were recently suggested as media for novel logic devices and on-chip interconnections [13].…”
Section: Introductionmentioning
confidence: 99%
“…This is just c N in (22) for N = 2 n , for any combination of N elements which uses each row and column exactly once, e.g. a pandiagonal, or one of Mayoral's more general orthogonal complement square sums [9], but obviously never a row or column.…”
Section: Proof Of the Pandiagonality Non-magic Propertymentioning
confidence: 99%
“…Fiue24Repeetto f ntutos instruction, Il, using the so-called implied or implicit addressing [GsMc75] where the data to be loaded is contained in the memory location next to the one storing instruction IV i.e., the address of the operand is derived by implication. The edge from node R 2 to OUT represents the transfer of the address of the operand from the program counter (R 2 ), (which is incremented by I by this time and points to the word next to the one storing instruction Ii), to the main memory address register, and the edge from IN to R I represents the data transfer from the main memory to register R I .…”
Section: Letmentioning
confidence: 99%
“…It is labeled I because the stack pointer must be incremented only after the data is pushed so that it * fpoints to the location on the stack where next data can be pushed. * Figure 2.5(c) shows how to represent a register load instruction 13 using direct addressing [GsMc75]. As shown in 1 I -Load register R from the main memory using immediate addressing.…”
mentioning
confidence: 99%