design of cyclic correlator for channel estimation in DTMB system Yuan Chen Yun Chen An Pan Jun Chen Xiaoyang Zeng State Key Lab of ASIC and System, Fudan University, Shanghai 201203, China

Abstract

In this paper, a cyclic-correlation based channel estimator is implemented for DTMB system. It exploits the quasi-cyclic structure of PN guard interval in DTMB system to obtain channel estimation results. Under SMIC 0.18 m standard CMOS technology, the proposed correlator can stably work at the frequency of 60MHz, and the circuit area is about 152k gates. Computational simulation shows that the proposed scheme has comparable performance with FFT-based channel estimator. Implementation results demonstrate that more than 3800 clock cycles and 82% design complexity reduction can be achieved without loss in performance of rms AMSE.