Design of Continuous-Time Σ∆ Modulators with Sine-Shaped Feedback DACs

Latiri, A.; Aboushady, Hassan; Beilleau, N.

doi:10.1109/iscas.2005.1465426

Cited by 9 publications

(7 citation statements)

References 9 publications

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“…In this technique, clock transitions take place when the sin-shaped feedback is at its maximum slope and hence results in a small charge error. To further reduce clock jitter noise, it may be more useful to use multiple sinshaped pulses per sampling period [22]. The maximum jitter noise reduction is 17dB, as reported in [22].…”

Section: Review Of Previous Workmentioning

confidence: 99%

“…But for sin-shaped DAC feedback, the circuit realization based on phase-locked loop is complex and difficult and it may dramatically increase power consumption. In addition, it is sensitive to loop delay, locking error and phase/amplitude noise of the feedback pulse itself [22,23]. Besides, extensibility of the sin-shaped DAC feedback to multi-bit operation is poor [7].…”

Section: Review Of Previous Workmentioning

confidence: 99%

“…Another reported technique to reduce clock jitter effects explores the use of sin-shaped DAC feedback [22,23] (an example of its waveform is also shown in Figure 2). In this technique, clock transitions take place when the sin-shaped feedback is at its maximum slope and hence results in a small charge error.…”

Section: Review Of Previous Workmentioning

confidence: 99%

“…To further reduce clock jitter noise, it may be more useful to use multiple sin-shaped pulses per sampling period [22]. The maximum jitter noise reduction is 17dB, as reported in [22]. But for sin-shaped DAC feedback, the circuit realization based on phase-locked loop is complex and difficult and it may dramatically increase power consumption.…”

Section: Review Of Previous Workmentioning

confidence: 99%

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Review and Comparison of Clock Jitter Noise Reduction Techniques for Lowpass Continuous-Time Delta-Sigma Modulators

Chang

Tang

2017

JLPEA

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Abstract:It is well known that continuous-time Delta-Sigma modulators are very sensitive to clock jitter effects. In literature, a number of techniques have been proposed to cope with them. In this brief, we present a detailed review and comparison of the reported techniques. While the effectiveness to reduce clock jitter effects may be of most importance in this comparison, we also consider other performance metrics such as circuit complexity and overhead to implement the technique, power consumption overhead of technique, synthesis complexity incurred in system-level design, extensibility of the technique from single-bit to multi-bit operation, and robustness to process variation. When clock jitter is relatively large, the fixed-width pulse feedback technique is most effective to reduce clock jitter effects among all techniques at high sampling frequency, while switched-capacitor-resistor and switched-shaped current techniques have best performance at medium frequency or below.

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Section: Review Of Previous Workmentioning

confidence: 99%

Section: Review Of Previous Workmentioning

confidence: 99%

Section: Review Of Previous Workmentioning

confidence: 99%

Section: Review Of Previous Workmentioning

confidence: 99%

See 2 more Smart Citations

Review and Comparison of Clock Jitter Noise Reduction Techniques for Lowpass Continuous-Time Delta-Sigma Modulators

Chang

Tang

2017

JLPEA

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“…So, the final expression of GH(z) can be obtained using the modified z-transform technique and residue theorem as described in [11].…”

Section: Subsampling Receivermentioning

confidence: 99%

On the RF subsampling continuous-time ΣΔ downconversion stage for multistandard receivers

Bechir¹,

Bouallègue²

2010

2010 2nd International Conference on Computer Engineering and Technology

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This paper deals with the design and analysis of a new RF subsampling downconversion front-end assigned to propose a multistandard receivers for next wireless generation standards. The RF subsampling front-end is based on continuous time (CT) bandpass ΣΔ modulator with sine-shaped feedback DAC. Much attention is given to frequency sampling selection and non idealities in subsampling CT-bandpass ΣΔ modulator. Thus, the mainly jitter effect on SNR degradation is investigated. Simulation results for a dual-mode GSM and WCDMA receiver based on RF subsampling fourth order CT-bandpass ΣΔ modulator show that the proposed topology can improve the SNR output measurement with low sampling rate.

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Nyquist-criterion based design of a CT ΣΔ-ADC with a reduced number of comparators

Maeye¹,

Rombouts²,

Weyten³

2009

Integration

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In this paper we present a prototype continuous time Σ∆-modulator in a 0.35 µm technology. The circuit has a 6-bit internal quantizer. Through the combination of a modified architecture and comparator interpolation this high quantizer resolution is achieved with only 15 comparators. However, it turns out that this approach imposes a severe speed constraint on the analog adder circuit. The modulator consists of a 3rd order loop and special care was taken in the design of the loop filter. The presented design has two particular features. First an explicit and controlled delay of 0.25 times the sampling period is introduced in the loop. Second, the Nyquist stability criterion and the vector gain margin are adopted to design a robustly stable modulator loop filter. This way our modulator does not require any tuning or trimming of the filter coefficients. Measurement results show a Peak SNR of 82 dB and a dynamic range of 85 dB for a bandwidth of 1.5 MHz.

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Design of Continuous-Time Σ∆ Modulators with Sine-Shaped Feedback DACs

Cited by 9 publications

References 9 publications

Review and Comparison of Clock Jitter Noise Reduction Techniques for Lowpass Continuous-Time Delta-Sigma Modulators

Review and Comparison of Clock Jitter Noise Reduction Techniques for Lowpass Continuous-Time Delta-Sigma Modulators

On the RF subsampling continuous-time ΣΔ downconversion stage for multistandard receivers

Nyquist-criterion based design of a CT ΣΔ-ADC with a reduced number of comparators

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