Design of CNTFET-Based Ternary ALU Using 2:1 Multiplexer Based Approach

Design and Implementation of a CNTFET-Based Ternary Logic Processor

“…Remark 6 : The 2:1 multiplexers used for the design of these functional modules are either PTI mux or NTI mux shown in Figure 9. These 2:1 multiplexers are same as the ones used in [9].…”

Design and Implementation of a CNTFET-Based Ternary Logic Processor

“…Hence, a set of two 3, 9 : 1 multiplexers are used to read out data from two registers of the TRF. Each 9 :1 multipliexer is designed using four 3 : 1 multiplexers as in [9], shown in Figure 8.…”

“…The proposed 3trit TALU implemented for the ternary processor is shown in Figure 7. The architecture of the proposed 3-trit TALU is similar to the 2 : 1 multiplexer based 2-trit TALU proposed in [9], that is, the 2-trit TALU in [9] is extended to a 3-trit TALU here. All the functional blocks like the adder-subtractor, multiplier, comparator and logic gates are designed using 2:1 multiplexer based design approach and can handle 3-trit data.…”

Design of ternary subtractor using multiplexers

“…Recently, various ternary logic circuits using the CNTFETs have been reported as they provide ideal stepwise current and voltage (I-V) characteristics (Sridharan et al, 2013;Mirzaee et al, 2014;Vudadha et al, 2012;Murotiya and Gupta, 2016;Gadgil and Vudadha, 2020). In (Sridharan et al, 2013), the design of CNTFET based three-trit and nine-trit adders is proposed.…”

“…From the analysis, it is noticed that the proposed circuits show 17% improvement in delay, 87% improvement in power consumption and 86% improvement in PDP. In (Gadgil and Vudadha, 2020), the 2:1 MUX-based adder-subtractor and multiplier modules are proposed. From the simulation results, it is noticed that 96% and 95% improvements in terms of power and PDP over the existing design styles.…”