Design of CMOS for 60GHz applications

Doan, C.H.; Emami, S.; Niknejad, Ali M.; Brodersen, R.W.

doi:10.1109/isscc.2004.1332783

Cited by 115 publications

(34 citation statements)

References 1 publication

Supporting

Mentioning

Contrasting

Order By: Relevance

“…In simulations the first stage has a conversion loss of about 4 dB, which should be added to the overall gain when comparing to non frequency converting PAs. Other published 60 GHz power amplifiers in CMOS show about 2-4 dB gain per stage [7], [11], [12], which our amplifiers also have in the last stage. For higher gain one or two more stages at 30 GHz or 60 GHz can be added to the PA.…”

Section: Measurement Resultssupporting

confidence: 62%

60 GHz 130-nm CMOS second harmonic power amplifiers

Wernehag

Sjöland

2008

APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems

View full text Add to dashboard Cite

Abstract-Two different frequency doubling power amplifiers have been measured, one with differential and one with singleended input, both with single-ended output at 60 GHz. The amplifiers have been implemented in a 1p8M 130-nm CMOS process. The resonant nodes are tuned to 30 GHz or 60 GHz using on-chip transmission lines, which have been simulated in ADS and Momentum.The measured input impedance of the single-ended PA is high at 250 Ω, and the differential input is similar, making the PA a suitable load for an oscillator in a fully integrated transmitter. The single-ended and differential input PA delivers 1 dBm and 3 dBm, respectively, of measured saturated output power to 50 Ω, both with a drain efficiency of 8%.

show abstract

Section: Measurement Resultssupporting

confidence: 62%

60 GHz 130-nm CMOS second harmonic power amplifiers

Wernehag

Sjöland

2008

APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems

View full text Add to dashboard Cite

show abstract

“…High power gain is easier to attain at lower frequencies, [7], [8] show two designs at about 30 GHz having gains of 7-8 dB. Other published 60 GHz power amplifiers in CMOS show about 2-4 dB gain per stage [9]- [11], which our amplifiers also have in the last stage. The 3-dB bandwidth is 5.9 GHz and 6.8 GHz, for the SI and DI.…”

Section: Simulation Resultsmentioning

confidence: 69%

Second harmonic 60-GHz power amplifiers in 130-nm CMOS

Wernehag

Sjöland

2007

2007 Ph.D Research in Microelectronics and Electronics Conference

View full text Add to dashboard Cite

Abstract-Two different frequency doubling power amplifier topologies have been compared, one with differential input and one with single-ended, both with single-ended output at 60 GHz. The frequency doubling capability is valuable from at least two perspectives, 1) the high frequency signal is on the chip as little as possible 2) the voltage controlled oscillator and power amplifier are at different frequencies easing the isolation of the two in a transceiver. The topologies have been simulated in a 1p8M 130-nm CMOS process.The resonant nodes are tuned with on-chip transmission lines. These have been simulated in ADS and compared to a standard Cadence component, tline3. The Cadence component gives a somewhat pessimistic estimation of the losses in the transmission line.The single ended input amplifier outputs a maximum of 3.7 dBm and draws 27 mA from a 1.2 V supply, while the one with differential input outputs 5.0 dBm and draws 28 mA. The 3-dB bandwidth of the amplifiers are 5.9 GHz and 6.8 GHz, respectively.

show abstract

“…Using typical notation for MoM analysis, the discretized electromagnetic (EM) problem is denoted as (1) and this can be expanded in terms of contributions from electric and magnetic currents as (2) where represents an interaction matrix, which measures the interaction between the expansion function and test function . The vectors and represent complex coefficients of the electric and magnetic current density, respectively.…”

Section: Modeling Approachmentioning

confidence: 99%

“…The use of vias is avoided in the measurement setup to minimize manufacturing uncertainties. Since the realization 1 Nelco N9000 PTFE Laminates, Park Electrochemical Corp. 2 Gore Speedboard C Prepreg Data Sheet, W. L. Gore & Associates. of vias requires an additional metallization step in the manufacturing process, the copper thickness increases and therefore, the metallization tolerances increase as well.…”

Section: A Measurement Setupmentioning

confidence: 99%

Balanced-Fed Planar Antenna for Millimeter-Wave Transceivers

Akkermans

Herben

Beurden

2009

IEEE Trans. Antennas Propagat.

View full text Add to dashboard Cite

Abstract-A balanced antenna design is presented that is tailored to broadband communication in the 60-GHz frequency band. The antenna can be realized in printed circuit-board technology, has a high radiation efficiency and can be used in array configurations. It is modeled with a method-of-moments implementation. The radiation efficiency is analyzed in detail, and design guidelines are given. Moreover, an optimization method is outlined that optimizes both antenna bandwidth and radiation efficiency. The antenna element and a circular antenna array have been realized. Measurements of these antennas are in good agreement with simulated results.Index Terms-Antenna arrays, antenna efficiency, antenna measurements, antenna optimization, millimeter-wave antenna, millimeter-wave antenna arrays, millimeter wave antennas, optimization methods.

show abstract

Design of CMOS for 60GHz applications

Cited by 115 publications

References 1 publication

60 GHz 130-nm CMOS second harmonic power amplifiers

60 GHz 130-nm CMOS second harmonic power amplifiers

Second harmonic 60-GHz power amplifiers in 130-nm CMOS

Balanced-Fed Planar Antenna for Millimeter-Wave Transceivers

Contact Info

Product

Resources

About