Design of Capacitorless DRAM Based on Polycrystalline Silicon Nanotube Structure

Abstract

In this study, a capacitorless one-transistor dynamic random-access memory (1T-DRAM) based on a polycrystalline silicon nanotube structure with a grain boundary (GB) is designed and analyzed using technology computer-aided design (TCAD) simulation. The proposed 1T-DRAM has the improved electrical performances because the outer gate (OG) and the inner gate (IG) effectively control the charges in the channel and body regions. IG has an asymmetric structure with an underlap (Lunderlap) region to reduce the Shockley-Read-Hall (SRH) recombination rate. In the proposed 1T-DRAM, the write "1" operation is performed by band-to-band tunneling between the OG and the IG. The proposed 1T-DRAM cell exhibited a sensing margin of 422 µA/µm and a retention time of 120 ms at T = 358 K.

Simulation of capacitorless DRAM based on polycrystalline silicon with a vertical underlap structure and a separated channel layer

“…Trapped electrons increase the potential barrier, impeding electron flow. As a result, the sensing margin and retention time reach their minimum values of 24.51 μA μm −1 and 1.991 s, respectively, in the 1 13) 14.10 251 2 27) 1.11 120 3 28) 0.39 10 4 29) 2.51 598 5 30) 8.73 704 6 31) 422 120 7 32) 12 170 8 33) 0. D-D′ case.…”

Bulk-fin field-effect transistor-based capacitorless dynamic random-access memory and its immunity to the work-function variation effect

“…Note that most 1T-DRAMs store holes in the body region near the metal gate. [20][21][22][23][24][25] However, the proposed JL bulk-FinFETbased 1T-DRAM device stores holes in H body-fin rather than H fin , as shown in Fig. 5(a).…”

“…This side effect is one of the critical issues encountered in the implementation of the HK/MG technology, and it not only affects logic transistors but also influences memory transistors. [20][21][22][23][24][25] So far, a few studies on WFV have been reported in the literature; [12][13][14][15][16][17][18][19] however, the impact of WFV on memory characteristics is yet to be investigated. Recently, Lee et al studied and investigated the effect of WFV on the transfer characteristics and memory performance of a gate-all-around junctionless (JL) field-effect transistor-based capacitorless dynamic random-access memory (1T-DRAM).…”

Bulk fin-type field-effect transistor-based capacitorless dynamic random-access memory with strong resistance to geometrical variations

“…SOI-like structures can be fabricated using polycrystalline silicon, but its grain boundaries affect the transfer characteristics and memory performance of such structures. [13][14][15][16] To address this issue, a junctionless bulk fin-type field-effect transistor (FinFET)-based (JLBF) 1T-DRAM was proposed herein that does not require a SOI or SOI-like structure. The proposed 1T-DRAM was fabricated by changing only the doping type of a typical junctionless bulk FinFET.…”