Design of Cache Controller for Multi-core Systems using Multilevel Scheduling Method

Bhure, Vipin; Padole, Dinesh

doi:10.1109/icetet.2012.47

Cited by 4 publications

(1 citation statement)

References 4 publications

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“…reduce both the bus traffic and the average access time. Moreover, associate a cache memory with each processor in the multiprocessor environment, is one of the most effective solutions to the bus bandwidth problem [3,4]. Since the processors in CMP have fast clock rate, the gap between processors speed and the relatively long time required to access the main memory becomes wider.…”

Section: Introductionmentioning

confidence: 99%

Design and Implementation of a Chip Multiprocessor with an Efficient Multilevel Cache System

El-Kustaban¹,

Qahtan²

2015

JST

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Computer designers utilize the recent huge advances in Very Large Scale Integration (VLSI) to get Chip Multiprocessor (CMP) by placing several processors on the same chip die. The CMP is the dominant architecture to improve the performance of the current computing systems. However, accessing a shared data by several processors is a primary challenge in CMP. The data consistency must be reached among all memory hierarchies to ensure correct behavior and higher performance. This paper, proposed a CMP with an efficient multilevel cache system, which enhances miss rate and latency (penalty) by designing and implementation of different write policies with two levels of cache. The proposed system is implemented and tested using Hardware Description Language (VHDL) on Altera’s FPGA chip. The results show that a combination of write-through without buffer for the first level and write-back for the second level offers a clear improvement on the multilevel cache system performance.

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Section: Introductionmentioning

confidence: 99%

Design and Implementation of a Chip Multiprocessor with an Efficient Multilevel Cache System

El-Kustaban¹,

Qahtan²

2015

JST

View full text Add to dashboard Cite

show abstract

Design and Implementation of a Chip Multiprocessor with an Efficient Multilevel Cache System

El-Kustaban

Qahtan

2015

J. sci. technol.

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Computer designers utilize the recent huge advances in Very Large Scale Integration (VLSI) to get Chip Multiprocessor (CMP) by placing several processors on the same chip die. The CMP is the dominant architecture to improve the performance of the current computing systems. However, accessing a shared data by several processors is a primary challenge in CMP. The data consistency must be reached among all memory hierarchies to ensure correct behavior and higher performance. This paper, proposed a CMP with an efficient multilevel cache system, which enhances miss rate and latency (penalty) by designing and implementation of different write policies with two levels of cache. The proposed system is implemented and tested using Hardware Description Language (VHDL) on Altera's FPGA chip. The results show that a combination of write-through without buffer for the first level and write-back for the second level offers a clear improvement on the multilevel cache system performance.

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Design and Implementation of Cache Memory With Fifo Cache-Control

ANAMIKA¹,

VINAY²,

SUMIT³

et al. 2018

JCS

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Design of Cache Controller for Multi-core Systems using Multilevel Scheduling Method

Cited by 4 publications

References 4 publications

Design and Implementation of a Chip Multiprocessor with an Efficient Multilevel Cache System

Design and Implementation of a Chip Multiprocessor with an Efficient Multilevel Cache System

Design and Implementation of a Chip Multiprocessor with an Efficient Multilevel Cache System

Design and Implementation of Cache Memory With Fifo Cache-Control

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