Design of bilayer graphene nanoribbon tunnel field effect transistor

Vobulapuram, Ramesh Kumar; Basha, Shaik Javid; Venkatramana, P; Mekala, Durga Prasad; Lingayath, Ujwala

doi:10.1108/cw-05-2020-0079

Cited by 10 publications

(3 citation statements)

References 32 publications

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“…50 nm length of GNR has been used in the channel region, and an N=16 A-GNR is used, where N is a number of a dimmer carbon atom. The GNR used in this device belongs to the n=3p+1 family, where p is a positive integer that behaves as a semiconductor [35]. Table 1: shows the detailed device parameter and specifications used for both structures, the proposed structures have identical architecture and dimensions, and only channel materials are different.…”

Section: Device Architecture and Simulation Set-upmentioning

confidence: 99%

“…QTX.MESH, QTY.MESH and QTUNN.DIR=ydir specific directions are included for tunneling direction in the simulator tools. The impact of generation and recombination on the account is activated by adding the Shockey-Reed-Hall recombination model (SRH) [35]. In addition, the concentration-mobility model (CONMOB) is also incorporated for low-field mobilities of charge carriers, and due to the importance of bandgap in the tunnel FET, the bandgap narrowing model (BGN) is needed to add to the simulation account [34].…”

Section: Device Architecture and Simulation Set-upmentioning

confidence: 99%

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Device and Circuit-Level Performance Evaluation of DG-GNR-DMG Vertical Tunnel FET

Liana

Tripathy

Choudhuri

et al. 2023

Preprint

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This work presents the comparative study of Graphene Nanoribbon (GNR) based channel Double Gate (DG) Dual Gate Material (DMG) Vertical tunnel FET performance with all Silicon material TFET. The two-dimensional material GNR has been proposed in the channel material to enhance the device performance due to its low bandgap, high mobility, and high saturation velocity. The proposed device's DC, RF, and circuit-level performance analysis has been carried out for the first time. GNR-based channel VTFET shows a better average subthreshold swing (SSAVG ) of 16 mV/decade compared to Si VTFET (36 mV/decade) at a drain voltage VDS=0.5 V. The study of temperature effects on the DC parameters is also included along with the analog/RF FOMs for the proposed two structures. In addition, the performances are compared with other reported works; it is observed that DG-GNR-DMG-VTFET offers better results than Si-based VTFET and other said TFET work. Finally, circuit-level analysis has been done by designing inverter and ring oscillator circuits for the proposed structures, and performance is compared in these two devices. The market-available Silvaco ATLAS TCAD simulator has been used for device-level simulation. Further, circuit-level analysis has been carried out in the Cadence Virtuoso tool using a look-up table-based Verilog-A model.

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Section: Device Architecture and Simulation Set-upmentioning

confidence: 99%

Section: Device Architecture and Simulation Set-upmentioning

confidence: 99%

Device and Circuit-Level Performance Evaluation of DG-GNR-DMG Vertical Tunnel FET

Liana

Tripathy

Choudhuri

et al. 2023

Preprint

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“…3. [18][19][20][21] Similar to the CMOSFET, the CNTFET has 4 regions in which undoped CNTs are positioned beneath the region of gate. Whereas, highly doped CNT is arranged under drain and source regions.…”

Section: Overview Of Ternary Logic and Cntfetmentioning

confidence: 99%

Design of Ternary Logic Circuits using Pseudo N-type CNTFETs

Ratankumar

2022

ECS J. Solid State Sci. Technol.

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A novel method is presented for design of ternary logic circuits for nanoelectronics applications. The ternary logic is a best alternative to the binary logic because it offers reduced interconnects, faster operating speed, and reduced chip area. The digital logic circuit designs are developed using Pseudo N-type carbon nanotube field effect transistors (CNTFETs). The threshold voltage of CNTFETs is altered by the CNT diameter that is defined by the chirality vector. The ternary inverters such as standard inverter, positive inverter, and negative inverter and ternary basic gates such as AND, NAND, OR, and NOR gates are designed. Furthermore, half adder circuits are developed, which assists in the development of complex circuit schematics. The proposed ternary schematics are designed and simulated using the HSPICE simulator. Finally, the performance of the proposed circuits are investigated in terms of delay, power dissipation, and power delay product and compared with the existing circuits. It is observed that the proposed circuits show average performance improvement up to 47.48% over the existing circuits.

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Exploring key aspects: Structure, properties, production, and oil & gas applications of graphene and its nanoribbons − A comprehensive review

Farag,

Helal

2023

Geoenergy Science and Engineering

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Design of bilayer graphene nanoribbon tunnel field effect transistor

Cited by 10 publications

References 32 publications

Device and Circuit-Level Performance Evaluation of DG-GNR-DMG Vertical Tunnel FET

Device and Circuit-Level Performance Evaluation of DG-GNR-DMG Vertical Tunnel FET

Design of Ternary Logic Circuits using Pseudo N-type CNTFETs

Exploring key aspects: Structure, properties, production, and oil & gas applications of graphene and its nanoribbons − A comprehensive review

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