Design of an MPEG-2 transport demultiplexor core

Anderson, Ron; Foster, Eric

doi:10.1147/rd.434.0521

Cited by 5 publications

(2 citation statements)

References 3 publications

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“…The basic functions a typical transport stream processor needs to support are packet synchronization, clock recovery, PID filtering, CRC checking, section filtering, bit-fields data processing, and data stream distributing [8] [9]. Packet synchronization is used to detect the boundaries of the incoming transport stream packets, and a simple scheme for this is provided by the MPEG-2 System Layer [1].…”

Section: A Software/hardware Partitioningmentioning

confidence: 99%

Flexible and Cost Effective Transport Stream Processor for DTV

Tsai¹,

Chien²

2007

2007 IEEE International Symposium on Circuits and Systems (ISCAS)

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Abstract-A flexible transport stream processor for DTV which is also designed under cost-effective consideration is proposed in this paper. A RISC micro-controller is allocated as the core of transport stream processor for flexibly extending or changing the functions of the transport stream processor. For the consideration of cost-effective design, the functions of the transport stream processor are partitioned into ones which are suitable for hardware implementation and the others suitable for the software executed by the micro-controller. Special enhancement of the instruction set of the micro-controller is proposed, with which the code efficiency of bit-level data-field processing could be improved. A general parsing engine for parsing grouping data-fields is also proposed. With the features described above, about 50% of total cost of transport stream processor with baseline functions can be saved.

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Section: A Software/hardware Partitioningmentioning

confidence: 99%

Flexible and Cost Effective Transport Stream Processor for DTV

Tsai¹,

Chien²

2007

2007 IEEE International Symposium on Circuits and Systems (ISCAS)

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“…Specifically, the IBM MPEG-2 Transport Demultiplexor is the core design referenced, and in-depth background on this architecture and on the set-top-box environment can be found in [9]. Specifically, the IBM MPEG-2 Transport Demultiplexor is the core design referenced, and in-depth background on this architecture and on the set-top-box environment can be found in [9].…”

Section: Introductionmentioning

confidence: 99%

Pseudorandom verification and emulation of an MPEG-2 transport demultiplexor

Reed

Thygesen

1999

IBM J. Res. & Dev.

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Pseudorandom verification and emulation of an MPEG-2 transport demultiplexor This paper describes two complementary approaches to performance verification for an MPEG-2 transport demultiplexor. The performance of such devices is difficult to verify during the design phase because of the many independent bus interfaces to which they may be connected and the numerous operating configurations that may be required. To address these problems, we have devised both a pseudorandom verification "environment," employing "controlled random" simulation, and a hardware-emulation platform based on field-programmable gate arrays (FPGAs). Actual hardware verification has shown the effectiveness of using these two methods together, and the overall approach can be applied to other design programs.

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A multigroup STC system

Kovacevic¹

2003 IEEE International Conference on Consumer Electronics, 2003. ICCE.

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Design of an MPEG-2 transport demultiplexor core

Cited by 5 publications

References 3 publications

Flexible and Cost Effective Transport Stream Processor for DTV

Flexible and Cost Effective Transport Stream Processor for DTV

Pseudorandom verification and emulation of an MPEG-2 transport demultiplexor

A multigroup STC system

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