Design of an Energy-Efficient CMOS-Compatible NoC Architecture with Millimeter-Wave Wireless Interconnects

Deb, Sujay; Chang, Ki-Ho; Yu, Xinmin; Sah, Suman P.; Cosic, Miralem; Ganguly, Amlan; Pande, Partha Pratim; Belzer, Benjamin J.; Heo, Deukhyoun

doi:10.1109/tc.2012.224

Cited by 173 publications

(116 citation statements)

References 38 publications

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“…As a reference, the 65-nm CMOS implementation presented in [35] [36]. The same authors increase the data rate by roughly tripling B for a total of 48 Gbps, while consuming 97.5 mW and 0.73 mm 2 .…”

Section: Phy: Towards Core-level Wireless Communicationmentioning

confidence: 99%

“…Seeking to avoid this, other works have explored more flexible ways to managing channel access. For instance, the protocol proposed in [36] uses the token passing strategy mentioned above. In [54], contention is avoided by exchanging control messages through the wired plane.…”

Section: Mac: Medium Access Control In Wnocmentioning

confidence: 99%

“…In [55], multiple narrow channels are used by different nodes to simultaneously send requests to a common receiver, which grants access to the data channel to only one of them. While these approaches reduce the complexity issues of using orthogonal channels, management is either latency-constrained [36] or not global [54], [55]. At the other end of the spectrum, contention-based schemes like ALOHA or CSMA have received less attention probably due to its random nature.…”

Section: Mac: Medium Access Control In Wnocmentioning

confidence: 99%

See 2 more Smart Citations

Scalability of Broadcast Performance in Wireless Network-on-Chip

Abadal

Mestres

Nemirovsky

et al. 2016

IEEE Trans. Parallel Distrib. Syst.

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Abstract-Networks-on-Chip (NoCs) are currently the paradigm of choice to interconnect the cores of a chip multiprocessor. For hundreds or thousands of cores, though, conventional NoCs may not suffice to fulfill the increasing on-chip communication requirements given that the performance of such networks actually drops as the number of cores grows, especially in the presence of multicast and broadcast traffic. This not only limits the scalability of current multiprocessor architectures, but also sets a performance wall that prevents the development of architectures that generate moderate-to-high levels of multicast. In this paper, a Wireless Network-on-Chip (WNoC) where all cores share a single broadband channel is presented. Such design is conceived to provide low latency and ordered delivery for multicast/broadcast traffic, in an attempt to complement a wireline NoC that will transport the rest of communication flows. To assess the feasibility of this approach, the network performance of WNoC is analyzed as a function of the system size and the channel capacity, and then compared to that of wireline NoCs with embedded multicast support. Based on this evaluation, preliminary results on the potential performance of the proposed hybrid scheme are provided, together with guidelines for the design of MAC protocols for WNoC.

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Section: Phy: Towards Core-level Wireless Communicationmentioning

confidence: 99%

Section: Mac: Medium Access Control In Wnocmentioning

confidence: 99%

Section: Mac: Medium Access Control In Wnocmentioning

confidence: 99%

See 1 more Smart Citation

Scalability of Broadcast Performance in Wireless Network-on-Chip

Abadal

Mestres

Nemirovsky

et al. 2016

IEEE Trans. Parallel Distrib. Syst.

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“…For the 20 mm Â 20 mm die, supposing the high resistivity silicon substrate ( ¼ 5 kΩ-cm) and oxide layer (e.g., AlN) of thickness 633 µm are used in hybrid WiNoC, the loss between antennas PL G is about 32 dB for 20 mm communication distance (about 9 dB at 1 mm distance) according to literature [12]. Since the power consumption of transceiver is found to be 36.7 mW at 16 Gbps for WiNoC, and thus the corresponding power consumption is 2.3 pJ/bit [14].…”

Section: Performance Evaluationmentioning

confidence: 99%

High-performance adaptive hybrid wireless NoC architecture based on improved congestion measurement

Yong-liang

et al. 2015

IEICE Electron. Express

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In view of the high energy consumption and latency problem due to multi-hop wired links between distant cores of traditional large-scale Network-on-Chip, a virtual torus-based adaptive wireless NoC architecture has been proposed when analyzing the existing several wireless NoC architectures. By not only adopting the automatic detection and dynamic bandwidth allocation mechanism to hot wireless link based on the sensing parameter for improved congestion measurement, but also designing the Dynamic Allocation Control Circuit Module (DACCM) for transmitter, the intra-chip topology and link bandwidth could be adaptively adjusted as different traffic patterns. Experimental results show that the proposed architecture has more significant latency improvement and energy saving under different traffic patterns or real application such benchmark as FFT.

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“…A plethora of works have proposed to use this technology for the implementation of a set of long-range links over a conventional NoC [8], [9], [10], [11]. This Wireless Networkon-Chip (WNoC) approach leverages the latency properties of wireless on-chip communication, attaining impressive performance and energy efficiency improvements with respect to traditional NoCs.…”

Section: Introductionmentioning

confidence: 99%

OrthoNoC: A Broadcast-Oriented Dual-Plane Wireless Network-on-Chip Architecture

Abadal

Torrellas

Alarcón

et al. 2018

IEEE Trans. Parallel Distrib. Syst.

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Abstract-On-chip communication remains as a key research issue at the gates of the manycore era. In response to this, novel interconnect technologies have opened the door to new Network-on-Chip (NoC) solutions towards greater scalability and architectural flexibility. Particularly, wireless on-chip communication has garnered considerable attention due to its inherent broadcast capabilities, low latency, and system-level simplicity. This work presents ORTHONOC, a wired-wireless architecture that differs from existing proposals in that both network planes are decoupled and driven by traffic steering policies enforced at the network interfaces. With these and other design decisions, ORTHONOC seeks to emphasize the ordered broadcast advantage offered by the wireless technology. The performance and cost of ORTHONOC are first explored using synthetic traffic, showing substantial improvements with respect to other wired-wireless designs with a similar number of antennas. Then, the applicability of ORTHONOC in the multiprocessor scenario is demonstrated through the evaluation of a simple architecture that implements fast synchronization via ordered broadcast transmissions. Simulations reveal significant execution time speedups and communication energy savings for 64-threaded benchmarks, proving that the value of ORTHONOC goes beyond simply improving the performance of the on-chip interconnect.

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Design of an Energy-Efficient CMOS-Compatible NoC Architecture with Millimeter-Wave Wireless Interconnects

Cited by 173 publications

References 38 publications

Scalability of Broadcast Performance in Wireless Network-on-Chip

Scalability of Broadcast Performance in Wireless Network-on-Chip

High-performance adaptive hybrid wireless NoC architecture based on improved congestion measurement

OrthoNoC: A Broadcast-Oriented Dual-Plane Wireless Network-on-Chip Architecture

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