Design of an advanced readout chip for silicon strip detectors

Zimmerman, T.; Sarraj, M.; Yarema, R.

doi:10.1109/23.256652

Cited by 15 publications

(4 citation statements)

References 6 publications

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“…2 Nanosim is a Synopsys Corp. simulation tool. 3 Calibre is a Mentor Graphics Corp. IC verification tool. 4 DivaLVS is a Cadence Design Systems IC verification tool.…”

Section: Measurementsmentioning

confidence: 99%

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SVX4: a new deep-submicron readout IC for the Tevatron collider at Fermilab

Krieger

Alfonsi

Bacchetta

et al. 2004

IEEE Trans. Nucl. Sci.

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SVX4 is the new silicon strip readout IC designed to meet the increased radiation tolerance requirements for Run IIb at the Tevatron collider. Devices have been fabricated, tested, and approved for production. The SVX4 design is a technology migration of the SVX3D design currently in use by CDF. Whereas SVX3D was fabricated in a 0.8-m radiation-hard process, SVX4 was fabricated in a standard 0.25-m mixed-signal CMOS technology using the "radiation tolerant by design" transistor topologies devised by the CERN RD49 collaboration. The specific cell layouts include digital cells developed by the ATLAS Pixel group, and full-custom analog blocks. Unlike its predecessors, the new design also includes the necessary features required for generic use by both the CDF and D0 experiments at Fermilab. Performance of the IC includes 20 MRad total dose tolerance, and 2000 e-rms equivalent input noise charge with 40-pF input capacitance, when sampled at 132-ns period with an 80-ns preamp risetime. At the nominal digitize/readout rate of 106/53 MHz, the 9 mm 6.3 mm die dissipates 2 mW/channel average at 2.5 V. A review of typical operation, details of the design conversion process, and performance measurements are covered.

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“…2 Nanosim is a Synopsys Corp. simulation tool. 3 Calibre is a Mentor Graphics Corp. IC verification tool. 4 DivaLVS is a Cadence Design Systems IC verification tool.…”

Section: Measurementsmentioning

confidence: 99%

“…DESIGN CONVERSION SVX4 keeps the same floorplan and low-impedance backside-grounding scheme that was proven successful for deadtimeless operation in SVX3D [3]. While reuse of the floorplan expedited the layout somewhat, several major blocks required redesign for implementation in the 0.25-m process.…”

mentioning

confidence: 99%

SVX4: a new deep-submicron readout IC for the Tevatron collider at Fermilab

Krieger

Alfonsi

Bacchetta

et al. 2004

IEEE Trans. Nucl. Sci.

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“…The VLPCs are light-sensitive solid-state photo-multipliers that convert the light into electrical signals. The analog front-end (AFE) boards [12] located on the VLPC cryostat split the electrical signal into two parts, one part is discriminated and sent out to the trigger system, the other part is stored in an analog pipeline for later (after L1 accept) digitization and readout after an L3 accept [13].…”

Section: The Central Track System Of Dømentioning

confidence: 99%

The central track trigger of the DO experiment

Hu¹,

Anderson²,

Angstadt³

et al. 2003

2003 IEEE Nuclear Science Symposium. Conference Record (IEEE Cat. No.03CH37515)

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The general purpose DØ collider detector, located at Fermi National Accelerator Laboratory, is operated in the high luminosity cm s and high-collision-rate environment (396 ns between beam crossings) of the upgraded Tevatron proton anti-proton accelerator. DØ uses a three-tiered trigger system to select events for offline storage and analysis. This paper describes the architecture and performance of the DØ central track trigger (CTT) system based on the new central fiber tracker, central preshower and forward preshower detectors, with emphasis on the interface to and integration with the second tier L2 Trigger system.

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“…The CAMEX chip used in ALEPH double side Si strip detectors has an architecture with four sampling switches [ 31. One of the recently developed front-end schemes [4] also uses the sampling of charge sensitive amplifier output.…”

Section: Introductionmentioning

confidence: 99%

Noise analysis of multiple correlated sampling

Kurchaninov

1997

Nuclear Instruments and Methods in Physics Research Section A:

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Design of an advanced readout chip for silicon strip detectors

Cited by 15 publications

References 6 publications

SVX4: a new deep-submicron readout IC for the Tevatron collider at Fermilab

SVX4: a new deep-submicron readout IC for the Tevatron collider at Fermilab

The central track trigger of the DO experiment

Noise analysis of multiple correlated sampling

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