Design of an accelerator-rich architecture by integrating multiple heterogeneous coarse grain reconfigurable arrays over a network-on-chip

Hussain, Waqar; Airoldi, Roberto; Hoffmann, Henry; Ahonen, Toni; Nurmi, Jari

doi:10.1109/asap.2014.6868647

Cited by 10 publications

(3 citation statements)

References 19 publications

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“…This architecture is based on the concept of CoPNoC (Co-Processing Network-on-Chip) [75], with the difference that the network topology used in this work is a star topology, where a central switch will allow parallel data transmission among PEs through a packet-switched method. Therefore, this case study is adequate for the SDR concept and Communication Systems on Chip (ComSoC) [76]- [80]. Before discussing the details and challenges of the design and implementation of the switch component, the NoC packet definition, the NoC communication protocol, and the specific requirements for this component are presented.…”

Section: Requirements For An Sdr Noc Switchmentioning

confidence: 99%

A Top-Down Modeling Approach for Networks-on-Chip Components Design: A Switch as Case Study

2023

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R. PARRA-MICHEL was born in Guadalajara, Mexico, in 1973. He received the B.Sc. degree in electronics and communications from the University of Guadalajara, in 1996, the M.Sc. degree in electrical engineering specializing in communications from CINVESTAV-IPN, Guadalajara, in 1998, and the Ph.D. degree in electrical engineering specialized in digital signal processing for communications from CINVESTAV-IPN, Mexico City, in 2003. He has collaborated with several companies and institutions either in academic or technology projects, such as Siemens, Lucent, Mabe, Mixbaal, Hewlett-Packard, and Intel. He is currently the Director of Guadalajara Unit, CINVESTAV-IPN, and the Head of the Wireless Communication Group. His research interests include modeling, simulation, estimation and equalization of communication channels, digital implementation of DSP algorithms for communication systems and on-chip networks.

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Section: Requirements For An Sdr Noc Switchmentioning

confidence: 99%

A Top-Down Modeling Approach for Networks-on-Chip Components Design: A Switch as Case Study

2023

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“…Também é possível encontrar uma configuração de arquitetura heterogênea que consiste em núcleos e aceleradores assimétricos e especializados, incluindo arquiteturas reconfiguráveis (Koutras et al, 2017;Duhem et al, 2015;Souza et al, 2016). No caso dos multicores com arquiteturas reconfiguráveis é possível encontrar tantos projetos que utilizam FPGAs (Watkins & Albonesi, 2010;Bouthaina et al, 2013), quanto CGRAs (Souza et al;Hussain, 2014), ou até mesmo ambas (Koenig et al, 2010).…”

Section: Trabalhos Relacionadosunclassified

Aceleradores Reconfiguráveis no Projeto Multicore: uma análise de custo versus benefício

Lopes

Pereira

2020

HOLOS

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A crescente evolução do software através de novas técnicas tem permitido o desenvolvimento de diversas soluções para atender a demanda da sociedade. Um exemplo atual é o avanço de técnicas de aprendizado de máquina para ser utilizadas em veículos autônomos, diagnósticos médicos, robôs, dentre outros. Diversas soluções de hardware têm surgido nos últimos anos para atender à essa demanda. Dentre essas soluções, os sistemas com múltiplos núcleos, chamados de multicores, estão entre as principais tendências. Porém, a busca por soluções de hardware não visa só o alto desempenho. É preciso levar em consideração outros aspectos como a eficiência energética e a área. Nesse cenário, a combinação de processadores com aceleradores reconfiguráveis tem sido amplamente explorada pelo fato destes últimos proporcionarem ganho de desempenho com redução de energia. Neste trabalho, pretendemos colaborar com o projeto de multicores investigando diferentes combinações de processadores com aceleradores reconfiguráveis. Como estudo de caso, combinamos processadores superescalares com arquiteturas reconfiguráveis de granularidade grossa e avaliamos três cenários. O primeiro é uma combinação de processadores e aceleradores que alcançam o mais alto desempenho possível para um conjunto de aplicações. O segundo é uma combinação de processadores e aceleradores definido por um limite de desempenho e o terceiro é limitado pela energia. Os experimentos mostram que é possível obter uma aceleração de mais de 2,5x para determinadas aplicações; economizar mais de 11% de energia com perda de 10% de aceleração e reduzir 30% de área com economia de 20% de energia.

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“…To the best of our knowledge, ours is the first work targeting optimizing architectural design for interfacing FPGA-based multi-accelerators with NoC-based multicore systems. Furthermore, our work is complementary to accelerator-rich architectures (i.e., the multicore systems with multiple accelerators) where ASIC blocks or CGRAs are distributed individually in an NoC framework as processing elements [13], [14].…”

Section: Related Workmentioning

confidence: 99%

Scalable Light-Weight Integration of FPGA Based Accelerators with Chip Multi-Processors

Lin

Sinha

Liang

et al. 2018

IEEE Trans. Multi-Scale Comp. Syst.

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Modern multicore systems are migrating from homogeneous systems to heterogeneous systems with accelerator-based computing in order to overcome the barriers of performance and power walls. In this trend, FPGA-based accelerators are becoming increasingly attractive, due to their excellent flexibility and low design cost. In this paper, we propose the architectural support for efficient interfacing between FPGA-based multi-accelerators and chip-multiprocessors (CMPs) connected through the network-on-chip (NoC). Distributed packet receivers and hierarchical packet senders are designed to maintain scalability and reduce the critical path delay under a heavy task load. A dedicated accelerator chaining mechanism is also proposed to facilitate intra-FPGA data reuse among accelerators to circumvent prohibitive communication overhead between the FPGA and processors. In order to evaluate the proposed architecture, a complete system emulation with programmability support is performed using FPGA prototyping. Experimental results demonstrate that the proposed architecture has high-performance, and is lightweight and scalable in characteristics.

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Design of an accelerator-rich architecture by integrating multiple heterogeneous coarse grain reconfigurable arrays over a network-on-chip

Cited by 10 publications

References 19 publications

A Top-Down Modeling Approach for Networks-on-Chip Components Design: A Switch as Case Study

A Top-Down Modeling Approach for Networks-on-Chip Components Design: A Switch as Case Study

Aceleradores Reconfiguráveis no Projeto Multicore: uma análise de custo versus benefício

Scalable Light-Weight Integration of FPGA Based Accelerators with Chip Multi-Processors

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