Design of an Accelerated Squarer Architecture Based on Yavadunam Sutra for Machine Learning

Ananthalakshmi, A.V.; Divyaparameswari, P.; Kanimozhi, P.

doi:10.1002/9781119910497.ch2

Machine Learning for VLSI Chip Design 2023

DOI: 10.1002/9781119910497.ch2

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Design of an Accelerated Squarer Architecture Based on Yavadunam Sutra for Machine Learning

A.V. Ananthalakshmi,

P. Divyaparameswari,

P. Kanimozhi

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Design of an Accelerated Squarer Architecture Based on Yavadunam Sutra for Machine Learning

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References 12 publications

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