Design of an 8-wide superscalar RISC microprocessor with simultaneous multithreading

Preston, R.P.; Badeau, R.; Bailey, Diana M.; Bell, Shane; Biro, Larry; Bowhill, William J.; Dever, D.E.; Felix, Stephen; Gammack, R.; Germini, V.; Gowan, M.K.; Gronowski, P.E.; Jackson, D.B.; Mehta, Shekhar; Morton, Shannon; Pickholtz, J.D.; Reilly, M.; Smith, M.J.

doi:10.1109/isscc.2002.992247

Cited by 27 publications

(17 citation statements)

References 4 publications

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“…Although not our focus in this work, our proposed technique can also be applied in other microprocessor architectures such as the out-of-order processors [25]. There, the renaming unit can assign infrequent registers to predetermined physical registers where the NBTI-induced stress is relaxed by our introduced hardware solution.…”

Section: Other Microrchitecturesmentioning

confidence: 99%

Stress balancing to mitigate NBTI effects in register files

Amrouch¹,

Ebi²,

Henkel³

2013

2013 43rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN)

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Negative Bias Temperature Instability (NBTI) is considered one of the major reliability concerns of transistors in current and upcoming technology nodes and a main cause of their diminished lifetime. We propose a new means to mitigate the effects of NBTI on SRAM-based register files, which are particularly vulnerable due to their small structure size and are under continuous voltage stress for prolonged intervals. The conducted results from our technology simulator demonstrate the severity of NBTI effects on the SRAM cells -especially when process variation is taken into account. Based on the presented analysis, we show that NBTI stress in different registers needs to be tackled using different strategies corresponding to their access patterns. To this end, we propose to selectively increase the resilience of individual registers against NBTI. Our technique balances the gate voltage stress of the two PMOS transistors of an SRAM cell such that both are under stress for approximately the same amount of time during operationthereby minimizing the deleterious effects of NBTI. We present mitigation implementations in both hardware and in software along with the incurred overhead. Through a wide range of applications we can show that our technique reduces the NBTIinduced reliability degradation by 35% on average. This is 22% better than current State-of-the-Art.

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Section: Other Microrchitecturesmentioning

confidence: 99%

Stress balancing to mitigate NBTI effects in register files

Amrouch¹,

Ebi²,

Henkel³

2013

2013 43rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN)

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“…The trend towards simultaneous multithreading also increases register count as separate architectural registers are needed for each thread. For example, the proposed eight-issue Alpha 21464 design had a regfile that occupied over five times the area of the 64 KB primary data cache [14].…”

Section: Introductionmentioning

confidence: 99%

Banked multiported register files for high-frequency superscalar microprocessors

Tseng¹,

Asanović²

2003

SIGARCH Comput. Archit. News

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Multiported register files are a critical component of high-performance superscalar microprocessors. Conventional multiported structures can consume significant power and die area. We examine the designs of banked multiported register files that employ multiple interleaved banks of fewer ported register cells to reduce power and area. Banked register files designs have been shown to provide sufficient bandwidth for a superscalar machine, but previous designs had complex control structures that would likely limit cycle time and add to design complexity. We develop a banked register file with much simpler and faster control logic while only slightly increasing the number of ports per bank. We present area, delay, and energy numbers extracted from layouts of the banked register file. For a four-issue superscalar processor, we show that we can reduce area by a factor of three, access time by 20%, and energy by 40%, while decreasing IPC by less than 5%.

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“…As contemporary mainstream processor architecture, SMT (Simultaneous Multithreading) [3] [4] [5] is capable of executing multiple instructions from different threads simultaneously. Through the excavation of the instruction-level parallelism within a single-thread and Inter-thread-level parallelism, SMT reduced the horizon waste and vertical waste.…”

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confidence: 99%

Boost the Performance of RMT

Yin

Jiang

2009

2009 International Conference on Information Engineering and Computer Science

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Simultaneous Multithreading Processor permits multiple issues from different threads at the same time, which provides nature support for fault-tolerance by executing threads redundantly. SRT is such architecture which detects faults by comparing the store instruction results between master threads and the copied slave threads. Later in SRTR, function of recovery is added. In SRT and SRTR, Instruction Queue (IQ) is a critical resource and slave threads can use IQ more efficiently, since master threads may encounter D-cache miss, while slave threads may not. Slave threads can get load instructions results from master threads and never commit store instructions results to storage. In master threads, instructions dependent on D-cachemiss-load instructions may stay in IQ for hundreds of cycles without any performance contributions. This paper proposed DDDI (Delay Dispatching Dependent Instructions) which means that instructions of master threads that dependent on unresolved D-cache-miss-load instructions can't be dispatched into IQ until the load instruction is completed. Experiments show that the method is effective for improving the IQ utilization and processor performance.

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Design of an 8-wide superscalar RISC microprocessor with simultaneous multithreading

Cited by 27 publications

References 4 publications

Stress balancing to mitigate NBTI effects in register files

Stress balancing to mitigate NBTI effects in register files

Banked multiported register files for high-frequency superscalar microprocessors

Boost the Performance of RMT

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