Design of a time-predictable multicore processor: The T-CREST project

Abstract

Real-time systems need to deliver results in time and often this timely production of a result needs to be guaranteed. Static timing analysis can be used to bound the worst-case execution time of tasks. However, this timing analysis is only possible if the processor architecture is analysis friendly.This paper presents the T-CREST processor, a real-time multicore processor developed to be time-predictable and an easy target for static worst-case execution time analysis. We present how to achieve time-predictability at all levels of the architecture, from the processor pipeline, via a network-on-chip, up to the memory controller. The main architectural feature to provide time predictability is to use static arbitration of shared resources in a time-division multiplexing way.

High performance and predictable memory controller for multicore mixed‐criticality real‐time systems

“…The validation of the mentioned intuition is shown in Section 4.2. [8] RR no high [9] RR no high [10] TDM and RR yes high [11] TDM yes low [12] EDF yes medium [13] RR no high [14] RR or TDM yes N/a [15] TDM and RM yes N/a [16] RR yes medium [17] RR no high [18] RR yes medium [19] TDM and RR yes high [20] TDM no low [21] TDM no low [22] TDM no low…”

“…Hence, the existence of a memory controller is essential to keep the predictability of the high-critical requests and the whole systems through providing an appropriate scheduling policy [6]. To preserve the predictability of the real-time systems, several memory controllers have been proposed [7][8][9][10][11][12][13][14][15][16][17][18][19][20][21][22]. Although all of them designed for real-time systems, their predictability is different.…”

“…The studies in [10,11,[19][20][21][22] eliminated the competition between tasks to use the shared memory by partitioning the memory access time to equal slots. The controllers presented in [11,[20][21][22] use time-triggered approach to schedule the memory requests. Using Time-Division Multiplexing (TDM) scheduling policy, they create time isolation for their tasks.…”

“…In [15], a requirement‐ and critical‐aware arbiter, named Carb , is proposed, which uses TDM and Rate Monotonic (RM) scheduling algorithms presented in [27]. The various memory controller [7–22] according their basic scheduling policy, supporting mixed‐criticality, and performance (inverse of the memory access time) feature or not are tabulated in Table 1.…”

“…Different memory controllers have been designed in the literature to provide predictability of the real‐time systems [7–22]. The predictability of different memory controllers is not the same, like their other features, e.g.…”