Design of a Refresh-Controller for GC-eDRAM Based FIFOs

Noy, Tzachi; Teman, Adam

doi:10.1109/tcsi.2020.2998582

Cited by 4 publications

(2 citation statements)

References 21 publications

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“…In the research article [9], author offer an original implementation of a single-well mixed 3T GC that uses the 28 nm FD-SOI technology. The proposed GC is equipped with body-bias control to increase the DRT by reducing leakage via the write port and to prolong the maximum operating frequency by forward body-biasing the read port.…”

Section: Literaturementioning

confidence: 99%

Design and Develop Efficient Arbitration Technique to Handle the Multiple Refresh Requests in Multi-Processor SoC

Shravan,

Fatima,

Sekhar

2023

IJRITCC

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Emerging memory technologies, such as Gain Cell-embedded Dynamic Random Access Memory (GC-eDRAM), play an essential part in the process of improving the overall performance of current multi-processor systems. GC-eDRAM, on the other hand, has its own set of distinct issues, particularly with regard to refresh operations. The number of cores and threads in contemporary processors continues to expand, which in turn leads to an increase in the number of concurrent refresh requests. This might cause contention, which in turn can lead to a possible performance decrease. In this article, we present an efficient arbitration method that was developed in order to precisely address the issues that are associated with numerous requests for a refresh in GC-eDRAM. This method takes use of the inherent parallelism of GC-eDRAM modules to make it possible to execute simultaneous refresh operations. As a result, contention is effectively reduced, and the overall performance of the system is improved. We provide a new arbitration method that prioritizes the pending refresh requests according to their level of urgency and optimizes the allocation of GC-eDRAM resources in order to guarantee that refresh operations are carried out in an effective manner. Our method modifies the arbitration priority in a dynamic manner according to the characteristics of the active workload. These characteristics include the request arrival rate, memory access patterns, and data location, among other considerations.

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Section: Literaturementioning

confidence: 99%

Design and Develop Efficient Arbitration Technique to Handle the Multiple Refresh Requests in Multi-Processor SoC

Shravan,

Fatima,

Sekhar

2023

IJRITCC

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“…A recently suggested approach called opportunistic refreshing [13] monitors the system operation and utilizes the two-ported capability of GC-eDRAM to apply refresh with no performance loss for typical workloads and operating scenarios. The refresh controller of [14], implements an algorithm that is able to completely hide the refresh of GC-eDRAM macros that are used to implement FIFO memories. However, none of these previously proposed works can ensure 100% availability with no performance loss for the random access case.…”

Section: Introductionmentioning

confidence: 99%

Refresh Algorithm for Ensuring 100% Memory Availability in Gain-Cell Embedded DRAM Macros

et al. 2021

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Gain-cell embedded DRAM (GC-eDRAM) is a dense, low power option for embedded memory implementation, supporting low supply voltages; however, it suffers from limited data retention time (DRT) and requires periodic refresh operations, limiting its use only to applications that can tolerate temporary memory blockages. In this work we propose a memory architecture based on a novel refreshing algorithm that provides 100% memory availability for the user, resulting in no performance loss for any possible access pattern. This approach allows the memory to have a standard SRAM interface ("vanilla interface"), supporting direct replacement of the SRAM memory with a GC-eDRAM memory. The algorithm/architecture was implemented in a 65 nm CMOS technology resulting in more than 20% area reduction compared with standard SRAM solutions, for large memory implementations.

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