Design of a Post-Matching Asymmetric Doherty Power Amplifier for Broadband Applications

Pang, Jingzhou; He, Songbai; Dai, Zhijiang; Huang, Chaoyi; Peng, Jun; You, Fei

doi:10.1109/lmwc.2015.2505651

Cited by 87 publications

(71 citation statements)

References 7 publications

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“…In this part, we will further enhance the efficiency and bandwidth of C‐DB DPA by optimizing R L . The postmatching technique has been employed to improve the performance of the continuous broadband DPA . In noncontinuous C‐DB DPA, the postmatching technique is introduced for the first time by deriving the expressions of Z C,BO and Z C,Sat with different phase delays θ c and θ p .…”

Section: Bandwidth Analysis Of C‐db Dpamentioning

confidence: 99%

A postmatching concurrent dual-band Doherty power amplifier with enhanced bandwidth

Meng

Zhu

Xia

et al. 2018

Int J RF Microw Comput Aided Eng

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In this article, a postmatching concurrent dual‐band (C‐DB) Doherty power amplifier (DPA) is proposed to enhance the bandwidth in each frequency band. The relationship between the phases of carrier and peaking impedance inverting networks (IINs) and the bandwidth of the C‐DB DPA is analyzed for the first time. By designing the carrier and peaking IINs with appropriate minimum phase delays, the bandwidth of C‐DB DPA can be enhanced and balanced in both frequency bands. Based on postmatching technique, load impedance at the combining point is optimized by comparing the DPA's bandwidth at back‐off and saturation. A high‐efficiency C‐DB DPA working at 2.0‐2.4 and 3.2‐3.6 GHz (400 MHz bandwidth each) is designed and fabricated based on commercial gallium nitride HEMTs to validate the proposed technique. Measurement results show that the DPA has a 6 dB back‐off efficiency of 54%‐57% and a saturated efficiency of 70%‐71% at 2.0‐2.4 GHz. At 3.2‐3.6 GHz, the efficiency of 52%‐55% at 6 dB back‐off and 65%‐71% at saturation can be obtained. Modulated signals are also employed to excite the DPA at the two bands. The DPA can achieve an average efficiency of more than 47% at 7 dB back‐off with excellent linearity by utilizing digital predistortion.

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Section: Bandwidth Analysis Of C‐db Dpamentioning

confidence: 99%

A postmatching concurrent dual-band Doherty power amplifier with enhanced bandwidth

Meng

Zhu

Xia

et al. 2018

Int J RF Microw Comput Aided Eng

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show abstract

“…To keep the increased circuit complexity at the minimum, different solutions to increase the HEPR while still maintaining a two-stage symmetrical DPA structure have been proposed. For example, in [44][45][46][47], an approach adopting asymmetrical drain bias voltage is presented. The main drawbacks of this solution are device under-utilization and increased bias circuit complexity.…”

Section: High-efficiency Power Rangementioning

confidence: 99%

High Efficiency Power Amplifiers for Modern Mobile Communications: The Load-Modulation Approach

et al. 2017

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Abstract:Modern mobile communication signals require power amplifiers able to maintain very high efficiency in a wide range of output power levels, which is a major issue for classical power amplifier architectures. Following the load-modulation approach, efficiency enhancement is achieved by dynamically changing the amplifier load impedance as a function of the input power. In this paper, a review of the widely-adopted Doherty power amplifier and of the other load-modulation efficiency enhancement techniques is presented. The main theoretical aspects behind each method are introduced, and the most relevant practical implementations available in recent literature are reported and discussed.

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“…With high data rate communication, there are demands of higher back‐off requirement and power requirement. There are currently few papers which have discussed the extended bandwidth DPA for higher back‐offs, upto 8‐9 dB, using symmetric packaged devices . In ref.…”

Section: Introductionmentioning

confidence: 99%

A wideband two‐stage Doherty power amplifier at high back‐off by exploring feasible design space

Ghosh

Rawat

2018

Int J RF Microw Comput Aided Eng

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This article explores a design space for bandwidth enhancement of two‐stage Doherty power amplifier for higher back‐off based on same devices. This design space analysis shows that for any back‐off level, a number of bandwidth enhancement solutions can be obtained with various combinations of design parameters for load combiner and load impedance. Therefore, the proposed scheme explores design space in terms of optimum design parameters for load combiner and load impedance for best bandwidth and realizability at a high back‐off. The proposed design methodology is validated with a two‐stage Doherty power amplifier using 25 W packaged Gallium Nitride High Electron Mobility Transistors. This Doherty power amplifier provides measured drain efficiency between 66% to 73.8% at saturation and 45% to 63.6% at 8‐9 dB output power back‐off from 1.7 to 2.025 GHz. Measurement with WCDMA signals shows that the adjacent channel power ratio is better than −46 dBc after applying digital predistortion.

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Design of a Post-Matching Asymmetric Doherty Power Amplifier for Broadband Applications

Cited by 87 publications

References 7 publications

A postmatching concurrent dual-band Doherty power amplifier with enhanced bandwidth

A postmatching concurrent dual-band Doherty power amplifier with enhanced bandwidth

High Efficiency Power Amplifiers for Modern Mobile Communications: The Load-Modulation Approach

A wideband two‐stage Doherty power amplifier at high back‐off by exploring feasible design space

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