Design of a Parallel Sampling Encoder for Analog to Information (A2I) Converters: Theory, Architecture and CMOS Implementation

Abstract

Abstract:We discuss the architecture and design of parallel sampling front ends for analog to information (A2I) converters. As a way of example, we detail the design of a custom 0.5 µm CMOS implementation of a mixed signal parallel sampling encoder architecture. The system consists of configurable parallel analog processing channels, whose output is sampled by traditional analog-to-digital converters (ADCs). The analog front-end modulates the signal of interest with a high-speed digital chipping sequence and integrates the result prior to sampling at a low rate. An FPGA is employed to generate the chipping sequences and process the digitized samples.

Sub-Sampling Framework Comparison for Low-Power Data Gathering: A Comparative Analysis

“…In this paper, we deal with CS when the signals are sampled at a sub-Nyquist frequency, resembling a technique that is referred to analog CS in the literature. The name derives from the fact that the sub-sampling is performed by dropping samples during the acquisition and analog-to-digital conversion (ADC) stage [ 32 ]. One notable example of this technique is in [ 33 ], where the effects of circuit imperfections in the analog compressive sensing architectures are discussed.…”

Design of configurable chipping sequence generator for high‐speed parallel samplers

“…Introduction: Recent theoretical advances in the field of compressed sensing have given rise to a number of intriguing data converter architectures that have the potential to provide sampling rates and resolutions greater than those that can be accomplished with traditional Nyquist-rate-based analogue-to-digital converters (ADCs) [1][2][3]. A necessary sub-system in these emerging data conversion architectures is the binary chipping sequence generator employed in the sampling encoder sub-system of the architecture [4][5][6]. The design of the chipping sequence generator for a single channel system is challenging because of the necessity of low-jitter output and it has proven the limiting functional block in implemented high-speed compressive samplers [7].…”