Design of a Multi-Core SoC with Configurable Heterogeneous 9 CPUs and 2 Matrix Processors

Nakajima, M.; Kondo, Hiroyuki; Okumura, N.; Masui, N.; Takata, Y.; Nasu, Takashi; Takata, Hiroshi; Higuchi, Takashi; Sakugawa, M.; Yoneda, Hideyuki; Fujiwara, Hidenori; Ishida, Kazuya; Ishimi, K.; Kaneko, Satoshi; Itoh, Teruyuki; Sato, Masayuki; Yamamoto, Osamu; Arimoto, Kazutami

doi:10.1109/vlsic.2007.4342717

Cited by 7 publications

(3 citation statements)

References 4 publications

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“…A developed multi-core LSI [11] implements an adaptive clock delay mechanism for AVS with wider voltage operation. The chip has multiple clock signals each for multiple CPUs and accelerators; each delay amount is controlled adaptively, by hardware and software.…”

Section: Adaptive Clock Delay For Avsmentioning

confidence: 99%

Low Power Platform for Embedded Processor LSIs

Shimizu

Arimoto

Nishii

et al. 2011

IEICE Trans. Electron.

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Various low power technologies have been developed and applied to LSIs from the point of device and circuit design. A lot more CPU cores as well as function IPs are integrated on a single chip LSI today. Therefore, not only the device and circuit low power technologies, but software power control technologies are becoming more important to reduce active power of application systems. This paper overviews the low power technologies and defines power management platform as a combination of hardware functions and software programming interface. This paper discusses importance of the power management platform and direction of its development.

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Section: Adaptive Clock Delay For Avsmentioning

confidence: 99%

Low Power Platform for Embedded Processor LSIs

Shimizu

Arimoto

Nishii

et al. 2011

IEICE Trans. Electron.

Self Cite

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“…User applications run on the general purpose OS. This technology is known as the Micro Clustering Model [3] [4].…”

Section: Aes-cmac 256-bit a High-definition Video-decode Acceleratormentioning

confidence: 99%

Heterogeneous multicore SoC for secure multimedia applications

Kondo

Nakajima

Otani

et al. 2008

2008 IEEE Custom Integrated Circuits Conference

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A heterogeneous multicore SoC (System on a Chip) has been developed for HD (High-Definition) multimedia applications that require secure DRM (Digital Rights Management). The SoC integrates three types of processors: two specific-purpose accelerators for a cipher and a high-resolution video decoding; one general-purpose accelerator (MX: Matrix processor); and three CPUs. This is how our SoC achieves high performance and low power consumption with hardware customized for video processing applications that process a large amount of data. To achieve secure data control, hardware memory management and software system virtualization are adopted. The security of the system is the result of the cooperation between the hardware and software on the system. Furthermore, a highly tamper-resistant system is provided on our SiP (System in a Package), through DDR memories and Flash ROM that contain confidential information in one package. This secure multimedia processor provides a solution to protect contents and to safely deliver secure sensitive information when processing billing transactions that involve digital content delivery. The SoC was implemented in the 90nm generic CMOS technology.

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“…The number of on-die thermal sensors keeps growing in very large scale integration (VLSI) systems to enable the DTM of chip functionalities [ 10 , 11 , 12 , 13 , 14 , 15 , 16 , 17 , 18 , 19 , 20 , 21 ], as shown in Figure 1 . The accuracy of on-chip sensor readings has a great influence on the effectiveness and reliability of DTM.…”

Section: Introductionmentioning

confidence: 99%

On-Line Temperature Estimation for Noisy Thermal Sensors Using a Smoothing Filter-Based Kalman Predictor

et al. 2018

Sensors

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Dynamic thermal management (DTM) mechanisms utilize embedded thermal sensors to collect fine-grained temperature information for monitoring the real-time thermal behavior of multi-core processors. However, embedded thermal sensors are very susceptible to a variety of sources of noise, including environmental uncertainty and process variation. This causes the discrepancies between actual temperatures and those observed by on-chip thermal sensors, which seriously affect the efficiency of DTM. In this paper, a smoothing filter-based Kalman prediction technique is proposed to accurately estimate the temperatures from noisy sensor readings. For the multi-sensor estimation scenario, the spatial correlations among different sensor locations are exploited. On this basis, a multi-sensor synergistic calibration algorithm (known as MSSCA) is proposed to improve the simultaneous prediction accuracy of multiple sensors. Moreover, an infrared imaging-based temperature measurement technique is also proposed to capture the thermal traces of an advanced micro devices (AMD) quad-core processor in real time. The acquired real temperature data are used to evaluate our prediction performance. Simulation shows that the proposed synergistic calibration scheme can reduce the root-mean-square error (RMSE) by 1.2 • C and increase the signal-to-noise ratio (SNR) by 15.8 dB (with a very small average runtime overhead) compared with assuming the thermal sensor readings to be ideal. Additionally, the average false alarm rate (FAR) of the corrected sensor temperature readings can be reduced by 28.6%. These results clearly demonstrate that if our approach is used to perform temperature estimation, the response mechanisms of DTM can be triggered to adjust the voltages, frequencies, and cooling fan speeds at more appropriate times.

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Design of a Multi-Core SoC with Configurable Heterogeneous 9 CPUs and 2 Matrix Processors

Cited by 7 publications

References 4 publications

Low Power Platform for Embedded Processor LSIs

Low Power Platform for Embedded Processor LSIs

Heterogeneous multicore SoC for secure multimedia applications

On-Line Temperature Estimation for Noisy Thermal Sensors Using a Smoothing Filter-Based Kalman Predictor

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