2011
DOI: 10.1016/j.aeue.2010.01.019
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Design of a mixed-signal digital CMOS fuzzy logic controller (FLC) chip using new current mode circuits

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Cited by 19 publications
(8 citation statements)
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“…To overcome this problem, we have used the idea that is proposed in [23] which is a current mirror in our proposed circuit.…”
Section: The Proposed Circuitmentioning
confidence: 99%
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“…To overcome this problem, we have used the idea that is proposed in [23] which is a current mirror in our proposed circuit.…”
Section: The Proposed Circuitmentioning
confidence: 99%
“…So far, different circuits in both WTA and LTA designs have been presented with their pros and cons. To the best of our knowledge other works up to now perform only one specific operation (Min or Max) [3,4,6,8,9,11,15,[18][19][20][21][22][23] or both operations together [1,10] that increases the power consumption and die area. In some cases such as FLC, to increase the controllability of circuit, two operations are required.…”
Section: Introductionmentioning
confidence: 97%
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“…Mainly, multipliers are required to calculate w i s i , secondly, adders are necessary to evaluate the sum of the terms and finally, a divider is needed to extract the weighted average of the singletons. Many simple methods have been published for multiplication and summation [7][8][9]. In spite of two previous blocks, divider is a more complex one to be designed in CMOS technology which appears as a bottleneck in the WAM implementation.…”
Section: Defuzzifier Circuitmentioning
confidence: 99%