Design of a Low-power Computational Unit using a Pipelined Vedic Multiplier

Mendez, Tanya; Nayak, Subramanya G.

doi:10.1109/iconat57137.2023.10080520

Cited by 2 publications

(1 citation statement)

References 14 publications

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“…To alleviate complex interconnections in the Wallace tree, Itoh implemented a 600 MHz two-stage multiplier [5]. To quest low power consumption, Tanya Mendez proposed a pipelined vedic multiplier [6]. Although it has lower power and delay, it does not fit RISC-V instructions.…”

Section: Introduction Risc-vmentioning

confidence: 99%

Design and Implementation of RISC-V Based Pipelined Multiplier

Sun,

Liu,

Zhang

et al. 2023

J. Phys.: Conf. Ser.

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Among the many microprocessors, RISC-V as an open-source instruction set is gradually gaining popularity among academia and industry. The performance of the multiplier in the microprocessor imposes constraints on the computational power of the processor. In order to improve the efficiency of multiplication instructions, a pipeline multiplier is implemented in this paper. Firstly, the partial product is generated using the Radix-4 booth. Secondly, the Wallace tree structure is used to accelerate the compression of the partial product. Then, a parallel prefix adder is used to calculate the resulting partial product to improve the timing. Finally, registers are added as a pipeline to achieve a high-efficiency multiplication calculation. With the operating voltage and temperature set to typical conditions, the integrated multiplier area is 50260.6 μm2, and the power consumption is 20.41 mW. The final frequency of the multiplier is 1 GHz in gate-level simulation.

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Section: Introduction Risc-vmentioning

confidence: 99%

Design and Implementation of RISC-V Based Pipelined Multiplier

Sun,

Liu,

Zhang

et al. 2023

J. Phys.: Conf. Ser.

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Hybrid Data Driven Clock Gating and Data Gating Technique for Better Saving Power in ALU RISC-V

Huan Vo

2024

IJEER

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The study proposes a hybrid data driven clock gating and data gating technique which is applied to ALU in RISC-V. By doing so, the proposed low power technique can improve the power saving efficiency. The proposed low power technique is compared with various low power techniques such as latch-free based clock gating, latch-based clock gating, single data driven clock gating, and single data gating. The results show that the proposed low power ALU saves 46.67% power consumption compared to original ALU. The proposed ALU also shows better saving power than the latch-free based clock gating, latch-based clock gating, sdata driven clock gating, and data gating from 10.84% to 22.23%. The comparison is also implemented on CPU which consists of memory, ALU and control unit. The proposed low power CPU saves 12.11% at least compared to the original CPU. However, the proposed low power CPU is reduced to 15.1% maximum frequency operation compared to the original CPU. The area overhead of the proposed ALU also increased to 33 LUTS (8.2%) and 2 registers (1.6%) compared to the original ALU.

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Design of a Low-power Computational Unit using a Pipelined Vedic Multiplier

Cited by 2 publications

References 14 publications

Design and Implementation of RISC-V Based Pipelined Multiplier

Design and Implementation of RISC-V Based Pipelined Multiplier

Hybrid Data Driven Clock Gating and Data Gating Technique for Better Saving Power in ALU RISC-V

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