Design of a Low Power Ultrasound Beamformer ASIC

Schwann, R.; Heselhaus, Thomas; Weiss, Oliver; Noll, Tobias G.

doi:10.1007/978-1-4757-3530-7_11

Cited by 1 publication

(2 citation statements)

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“…In the late 1990s it was replaced by digital delay lines. Because until now only hardware could satisfy the requirement for rapid processing of signals from many channels in parallel, digital beamforming has been historically implemented in ASICs [6] or FPGAs [7].…”

Section: Digital Beamforming Processingmentioning

confidence: 99%

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Medical ultrasound digital beamforming on a massively parallel processing array platform

Chen¹,

Butts²,

Budlong³

2008

SPIE Proceedings

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Digital beamforming has been widely used in modern medical ultrasound instruments. Flexibility is the key advantage of a digital beamformer over the traditional analog approach. Unlike analog delay lines, digital delay can be programmed to implement new ways of beam shaping and beam steering without hardware modification. Digital beamformers can also be focused dynamically by tracking the depth and focusing the receive beam as the depth increases. By constantly updating an element weight table, a digital beamformer can dynamically increase aperture size with depth to maintain constant lateral resolution and reduce sidelobe noise. Because ultrasound digital beamformers have high I/O bandwidth and processing requirements, traditionally they have been implemented using ASICs or FPGAs that are costly both in time and in money.This paper introduces a sample implementation of a digital beamformer that is programmed in software on a Massively Parallel Processor Array (MPPA) . The system consists of a host PC and a PCI Express-based beamformer accelerator with an Ambric Am2045 MPPA chip and 512 Mbytes of external memory. The Am2045 has 336 asynchronous RISC-DSP processors that communicate through a configurable structure of channels, using a self-synchronizing communication protocol.

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Section: Digital Beamforming Processingmentioning

confidence: 99%

“…Because ultrasound requires massive computing power to process large amounts of data in parallel, up to now ultrasound designers typically have taken an approach that uses an ASIC [1] or FPGA [2] at the expense of design time, engineering resources, and ASIC fabrication cost. Yet the resulting implementation is inflexible and non-reusable.…”

Section: Introductionmentioning

confidence: 99%