Design of a Low Complexity and Fast Hardware Architecture for Digital Image Watermarking in FWHT Domain on FPGA

Ghosh, Sudip; Biswas, Arijit; Maity, Santi P.; Rahaman, Hafizur

doi:10.1109/ised.2014.22

Cited by 3 publications

(2 citation statements)

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“…In the watermark_prepare module, as shown in Figure 8a, the DC component and image texture of the block need to be calculated. According to (10) and (24), Y channel data are simultaneously sent to a sixteen-input adder tree and the grain analysis module to get the DC component and L, respectively. Since these two operations have no relevance, they are also carried out in parallel to reduce latency.…”

Section: Parallel Computing and Pipelinementioning

confidence: 99%

“…Although spatial-domain watermarking methods are easy to implement and usually require less computational resources, they are not robust enough to attacks such as JPEG compression and geometry attacks [19]. As for the transform domain, image watermarking methods are mostly carried out in the discrete cosine transform (DCT) domain [1,7,13], the discrete Fourier transform (DFT) domain [20][21][22] or the discrete wave transformation (DWT) domain [9,[22][23][24][25][26]. Watermarking in the transform domain is often based on the human vision system (HVS) [2,4,10,27,28] model to achieve invisibility and robustness.…”

Section: Introductionmentioning

confidence: 99%

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A Hidden DCT-Based Invisible Watermarking Method for Low-Cost Hardware Implementations

et al. 2021

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This paper presents an invisible and robust watermarking method and its hardware implementation. The proposed architecture is based on the discrete cosine transform (DCT) algorithm. Novel techniques are applied as well to reduce the computational cost of DCT and color space conversion to achieve low-cost and high-speed performance. Besides, a watermark embedder and a blind extractor are implemented in the same circuit using a resource-sharing method. Our approach is compatible with various watermarking embedding ratios, such as 1/16 and 1/64, with a PSNR of over 45 and the NC value of 1. After Joint Photographic Experts Group (JPEG) compression with a quality factor (QF) of 50, our method can achieve an NC value of 0.99. Results from a design compiler (DC) with TSMC-90 nm CMOS technology show that our design can achieve the frequency of 2.32 GHz with the area consumption of 304,980.08 μm2 and power consumption of 508.1835 mW. For the FPGA implementation, our method achieved a frequency of 421.94 MHz. Compared with the state-of-the-art works, our design improved the frequency by 4.26 times, saved 90.2% on area and increased the power efficiency by more than 1000 fold.

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Section: Parallel Computing and Pipelinementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A Hidden DCT-Based Invisible Watermarking Method for Low-Cost Hardware Implementations

et al. 2021

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Implementation of image copyright protection tool using hardware-software co-simulation

Roy

Basu²,

Chattopadhyay

et al. 2020

Multimed Tools Appl

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A Digital Watermarking Encryption Technique Based on FPGA Cloud Accelerator

2020

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Digital watermarking has the properties such as invisibility and anti-aggression, so the digital watermarking technology has been widely used in copyright protection, information hiding. The watermarking technology takes into account the invisibility and robustness of the watermark by controlling the embedding intensity and position of the watermark mainly in the transformation domain. In this paper, discrete cosine transform (DCT) is adopted to transform the given image from spatial domain to frequency domain for adding watermark information. In order to meet the demands of image watermarking batch processing and cloud processing in the future, this paper optimized the DCT algorithm and the data precision, and successfully deployed the designed accelerator kernel on the FPGA cloud platform to speed up the processing of watermarking. The implementation of data processing based on cloud platform is the development trend of big data era. The cloud platform adopted in this paper is based on the OpenCL heterogeneous architecture combining CPU and FPGA. The cloud-based implementation makes digital watermarking application highly extensible, widely shareable, and more secure. The whole system implements a series of complete cloud processes including image decoding, image preprocessing, watermark embedding, and watermarked image encoding. The watermarking algorithm is accelerated by the efficient parallel computing capabilities of FPGA. It can be seen that the result of acceleration is remarkable, providing the state-of-the-art throughput of 1.676 GBps and the highest processing speed of 937 FPS for 800 × 800 sized colorimage. INDEX TERMS Cloud services, parallel operation, integer DCT, data encryption and watermarking, heterogeneous architecture.

show abstract

Design of a Low Complexity and Fast Hardware Architecture for Digital Image Watermarking in FWHT Domain on FPGA

Cited by 3 publications

References 10 publications

A Hidden DCT-Based Invisible Watermarking Method for Low-Cost Hardware Implementations

A Hidden DCT-Based Invisible Watermarking Method for Low-Cost Hardware Implementations

Implementation of image copyright protection tool using hardware-software co-simulation

A Digital Watermarking Encryption Technique Based on FPGA Cloud Accelerator

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