Design of a high‐speed RSA encryption processor based on the residue table for redundant binary numbers

Abstract

SUMMARYThe RSA cryptosystem plays an important role in ensuring the security of network communications, although it has the drawback that much time is required for encryption/decryption. This paper presents a high-speed RSA encryption processor employing highly parallel operation based as much as possible in the hardware technology as follows: (1) All of the arithmetic circuits required for encryption/decryption are implemented in the form of redundant binary numbers. (2) Residue calculation is performed by table look-up in a hardware table built in the processor. The table look-up is done in the form of redundant binary numbers. The operation speed of the proposed processor is found to be 60 times that of usual processors when the key length N is 1024 bits. Also, the order of the encryption time of the processor is O (NlogN). The chip size of the processor is estimated as (4.3 × 10 5

A novel dynamic multi-service multi-grade encryption scheme used in EPON

“…Real-time services (RTS) such as video on demand (VOD), high-definition television (HDTV) and video conferencing with so a small delay requirement than safety that the simplest possible security encryption algorithms should be chosen like DES, 3DES [9,10] General data services (GDS) including web browsing, uploading and downloading and FTP with relatively modest requirements for the quality of service (QoS) and safety, so the encryption algorithm selected can be moderate in complexity and security as well as reducing consumption like RSA, AES [11][12][13][14][15] Confidential data services (CDS) , a relatively low proportion of traffic , are characterized by a low latency but a high security requirements such as carry-key information of control frame in…”