Design of a high speed string matching co-processor for NLP

Murty, V.S.; Raj, P. C. Reghu; Raman, Shanmuganathan

doi:10.1109/icvd.2003.1183134

Cited by 3 publications

(4 citation statements)

References 8 publications

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“…Limited work has been reported in the literature to present hardware implementations of MA systems in general and for Arabic language in specific. Murty et al (2003), and like many investigations, presented the design of high-speed string matching co-processor for NLP. Other reported work comprises fast VLSI implementations for approximate string matching (Grossi, 1992), FPGA-based co-processor for text extraction (Ratha et al, 2000), and ASIC design of a high-speed unit for NLP to match inputs with lexical entries (Raman and Shaji, 1995).…”

Section: Research Objectivesmentioning

confidence: 95%

“…Non-pipelined Pipelined language. In the literature, application-specific hardware systems are mainly proposed to implement high-speed string matching algorithms (Murty et al, 2003;Grossi, 1992;Ratha et al, 2000;Raman and Shaji, 1995). With no doubt, the developed hardware cores for Arabic language can be refined to suite Applicationspecific Integrated Circuits (ASICs).…”

Section: General Evaluationmentioning

confidence: 99%

“…The current investigation is pioneering in the fact that limited work has been reported in the literature aiming at creating parallel hardware cores suitable for FPGA implementations and for Arabic language. In the literature, application-specific hardware systems are mainly proposed to implement high-speed string matching algorithms (Murty et al, 2003;Grossi, 1992;Ratha et al, 2000;Raman and Shaji, 1995). With no doubt, the developed hardware cores for Arabic language can be refined to suite Applicationspecific Integrated Circuits (ASICs).…”

Section: General Evaluationmentioning

confidence: 99%

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Parallel hardware for faster morphological analysis

Damaj

Imdoukh

Zantout

2018

Journal of King Saud University - Computer and Information Scie

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Hardware design FPGAs a b s t r a c tMorphological analysis of Arabic language is computationally intensive, has numerous forms and rules, and intrinsically parallel. The investigation presented in this paper confirms that the effective development of parallel algorithms and the derivation of corresponding processors in hardware enable implementations with appealing performance characteristics. The presented developments of parallel hardware comprise the application of a variety of algorithm modelling techniques, strategies for concurrent processing, and the creation of pioneering hardware implementations that target modern programmable devices. The investigation includes the creation of a linguistic-based stemmer for Arabic verb root extraction with extended infix processing to attain high-levels of accuracy. The implementations comprise three versions, namely, software, non-pipelined processor, and pipelined processor with high throughput. The targeted systems are high-performance multi-core processors for software implementations and high-end Field Programmable Gate Array systems for hardware implementations. The investigation includes a thorough evaluation of the methodology, and performance and accuracy analyses of the developed software and hardware implementations. The developed processors achieved significant speedups over the software implementation. The developed stemmer for verb root extraction with infix processing attained accuracies of 87% and 90.7% for analyzing the texts of the Holy Quran and its Chapter 29 -Surat Al-Ankabut. Ó 2017 The Authors. Production and hosting by Elsevier B.V. on behalf of King Saud University. This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/).

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Section: Research Objectivesmentioning

confidence: 95%

Section: General Evaluationmentioning

confidence: 99%

Section: General Evaluationmentioning

confidence: 99%

See 1 more Smart Citation

Parallel hardware for faster morphological analysis

Damaj

Imdoukh

Zantout

2018

Journal of King Saud University - Computer and Information Scie

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“…Recent advances in field-programmable gate array (FPGA) technology, such as drastic increases in the amount of logic resources and the inclusion of embedded hardware components, have made FPGAs viable platforms for accelerating scientific computing applications [7,18,25,28,33,35,37]. Unlike the PRAM-based software parallel prefix algorithms that suffer from the communication cost between arbitrary pairs of processors using shared or distributed memory modules during the computation, the special purpose hardware for the parallel prefix computation can reduce the traffic significantly.…”

mentioning

confidence: 99%

Reconfigurable hardware solution to parallel prefix computation

Park

Dai

2007

J Supercomput

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This paper presents the design and implementation of an efficient reconfigurable parallel prefix computation hardware on field-programmable gate arrays (FPGAs). The design is based on a pipelined dataflow algorithm, and control logic is added to reconfigure the system for arbitrary parallelism degree. The system receives multiple input streams of elements in parallel and produces output streams in parallel. It has an advantage of controlling the degree of parallelism explicitly at run time. The time complexity of the design is O(d + (N − d)/d), where d and N are parallelism degree and stream size, respectively. When the stream size is sufficiently larger than the initial trigger time of the pipeline (d), the time complexity becomes O(N/d). Unlike the prefix computation circuits found in the literature, the design is scalable for different problem sizes including unknown sized data. The design is modular based on a finite state machine, and implemented and tested for target FPGA devices Xilinx Spartan2S XC2S300EFT256-6Q and XC2S600EFG676-6.

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Design of a Language-Independent Parallel String Matching Unit for NLP

Murty

Raj

Raman

2003 IEEE International Workshop on Computer Architectures for Machine Perception

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Design of a high speed string matching co-processor for NLP

Cited by 3 publications

References 8 publications

Parallel hardware for faster morphological analysis

Parallel hardware for faster morphological analysis

Reconfigurable hardware solution to parallel prefix computation

Design of a Language-Independent Parallel String Matching Unit for NLP

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