2020 IEEE 1st China International Youth Conference on Electrical Engineering (CIYCEE) 2020
DOI: 10.1109/ciycee49808.2020.9332742
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Design of a High Efficiency Buck Converter

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Cited by 5 publications
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“…Smaller devices' size allows for smaller chip area and lower switching loss due to smaller parasitic capacitance. The sizing W/L of the output transistors MPOW1 and MPOW2 depends on the tradeoff between conduction loss and switching loss, which are 2 major power loss components in the power stage of the buck converter [51]. The equations for switching loss and conduction loss can be written as follows.…”
Section: Power Stagementioning
confidence: 99%
“…Smaller devices' size allows for smaller chip area and lower switching loss due to smaller parasitic capacitance. The sizing W/L of the output transistors MPOW1 and MPOW2 depends on the tradeoff between conduction loss and switching loss, which are 2 major power loss components in the power stage of the buck converter [51]. The equations for switching loss and conduction loss can be written as follows.…”
Section: Power Stagementioning
confidence: 99%