Design of a gigabit ATM switch

Abstract

This report describes the design and implementation of a gigabit ATM switching system supporting link rates from 150 Mb/s to 2.4 Gb/s, with a uniquely e cient multicast switch a r c hitecture that enables the construction of systems with essentially constant per port costs for con gurations ranging from 8 to 4096 ports and system capacities approaching 10 Tb/s. The system design supports many-to-one and many-to-many forms of multicast, in addition to the usual one-to-many. It also provides multicast virtual paths, constant time con guration of multicast connections and an e cient p a c ket-level discard method, that can achieve 100% link e ciencies, without large bu ers.

Terabit Burst Switching

“…For comparison, the system of 12] can be implemented for approximately $350 per Gb/s of capacity, using 1.2 Gb/s links. 3 So, even under fairly pessimistic component c o s t assumptions, the system can provide competitive cost/performance, as well as high end performance and total capacity. Using the low cost estimates, the reference system is about a factor of seven better than the system of 12].…”

“…This, in turn means that the data channels must operate at prescribed data rates. If, on the other hand, a communication channel can be switched entirely in the optical domain from end-to-end without re-timing, 3 In this comparison, 1.2 Gb/s links are used, since there are inexpensive, integrated transmission components at 1.2 Gb/s, while there are no comparable components currently at 2.4 Gb/s. If currently available OC-48 SONET transmission components were used, the cost per Gb/s would increase by $500 to $1,000.…”

Maximum weight matching dispatching scheme in buffered Clos-network packet switches

“…A gigabit ATM (asynchronous transfer mode) switch using buffers in the second-stage was presented in [3]. In this architecture, every cell is randomly distributed from the firststage to the second-stage modules to balance the traffic load in the second-stage.…”

“…Since there are no buffers in the second-stage modules to resolve contention, dispatching cells from the first stage to the second stage becomes an important issue. A random dispatching (RD) scheme is used for cell dispatching from the first stage to the second stage [4], as adopted in the case of the buffered second-stage modules in [3]. However, RD is not able to achieve a high throughput unless the internal bandwidth is expanded, because the contention at the second stage cannot be avoided.…”

The Gemini interconnect: Data path measurements and performance analysis

“…The primary cause for the poor performance is excessive blocking in the Banyan network using the simple setup-teardown protocol. 2 Consider the 4 4 n e t work depicted in Figure 17 for example. Terminal S1 is sending an optical message to terminal D3, and terminal S4 is sending an optical message to terminal D2.…”