At present, line-scan CCD camera with camera link output cannot be connected with the video ports of DM642. To this issue, based on the detailed analysis of the camera link interface protocol, three specialized chips were chose for level conversion; More over, a FIFO buffer has been designed in FPGA combined the camera specification and sequential. It solves the interface problem between camera and DM642, that is the data butter of the different clock domains. The design has achieved the control of the line-scan CCD camera and sampling of CCD signal. The tests indicate that, the interface circuit can sample effectively. Moreover, it has Laid the foundation for further analyzing and processing of image data.