Design of a CMOS PFD-CP module for a PLL

Abstract

This paper introduces a modified design of Phase frequency detector (PFD) with reduced dead zone and improved charge pump (CP) with reduced current mismatch for a Phase Locked Loop (PLL). Three modified PFD circuits are proposed, designed, simulated, and the results are analyzed considering dead zone as a constraint. Design of pass transistor logic network plays a part in the diminution of the dead zone. Further, an improved design of CP is proposed to reduce current mismatch. It is achieved by placing the single ended differential amplifier in currentvoltage feedback configuration which offers high output impedance. Simulations are performed using T-SPICE, implemented in IBM 0.13 µm technology under 1.3 V power supply. Results show that the modified PFD design has a dead zone of 0.3 ns and the current mismatch decrements to 0.1 µA in an improved CP design.

Optimisation and Performance Computation of a Phase Frequency Detector Module for IoT Devices

“…www.aetic.theiaer.org Over the decades, researchers have been trying to employ various optimisation techniques to escalate the performance of PFD. In 2015, Anushkannan [14] used pass transistors to optimise power consumption, however, the operational frequency was very low. In 2016, Gholami [15] used transmission gate-based PFD, which achieved relatively higher operational frequency, but the power consumption was excessively high.…”

A Modified PFD Based PLL with Frequency Dividers in 0.18-µm CMOS Technology

“…The PLL operates at a high frequency, and then the circuit delivers more power, and thereby it increases the area. In order to reduce dead zone, three modified circuits were designed, simulated and the results were observed based on pass transistor logic [10]. Now, a modified PFD is proposed to obtain null dead zone.…”