Design of a Class-F Power Amplifier with GaN Device Model and Reflection Data

Alemdag, Merve; Kaçar, Fırat; Kılınç, Sedat

doi:10.1080/03772063.2020.1859950

Cited by 4 publications

(3 citation statements)

References 15 publications

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“…e power-added efficiency (PAE) of the proposed HPA is 29.8%, which can be easily understood by η � (P out − P in )/ P dc x100, where P in and P out represent the input power and output power, respectively. eoretically, only class F power amplifier has the ability to achieve 100% of PAE [27], which is not possible for the case of Doherty due to different classes of PA. However, both biasing voltages at subthreshold regions are optimized at perfect matching to achieve the backoff level at 29.8% PAE.…”

Section: Power Dissipation Power-added Efficiency (Pae) and Gate Biasing For Enhanced Power Backoff Efficiencymentioning

confidence: 99%

Design and Optimization of 2.1 mW ULP Doherty Power Amplifier with Interstage Capacitances Using 65 nm CMOS Technology

Akhter

Amin

2021

Mathematical Problems in Engineering

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This research proposed the design and calculations of ultra-low power (ULP) Doherty power amplifier (PA) using 65 nm CMOS technology. Both the main and the peaking amplifiers are designed and optimized using equivalent lumped parameters and power combiner models. The operation has been performed in RF-nMOS subthreshold or triode region to achieve ultra-low power (ULP) and to improve the linearity of the overall power amplifier (PA). The novel design consumes a DC power of 2.1 mW, power-added efficiency (PAE) of 29.8%, operating at 2.4 GHz band, and output referred 1 dB compression point at 4.1dBm. The simulation results show a very good capability of drive current, high gain, and very low input and output insertion losses.

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Section: Power Dissipation Power-added Efficiency (Pae) and Gate Biasing For Enhanced Power Backoff Efficiencymentioning

confidence: 99%

Design and Optimization of 2.1 mW ULP Doherty Power Amplifier with Interstage Capacitances Using 65 nm CMOS Technology

Akhter

Amin

2021

Mathematical Problems in Engineering

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“…To improve the efficiency of PA, harmonic engineering technology has become a hot topic. Traditional high‐efficiency mode PAs such as class‐E 2 and class‐F 3 can only work in narrowband mode. Giannini and Scucchia 4 studied the effect of impedance at the second and third harmonics of a distributed element matching networks on efficiency.…”

Section: Introductionmentioning

confidence: 99%

“…The designs in References 2,3,7–9 are based on the 10‐W devices, and the output power is higher than 10 W in the target frequency band. To obtain higher output, Sharma et al 10 used a 25‐W device to design.…”

Section: Introductionmentioning

confidence: 99%

Design of a broadband power amplifier based on high‐efficiency impedance space

Wang

Yao

Xiong

et al. 2023

Circuit Theory & Apps

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SummaryWe propose a broadband high‐efficiency power amplifier (PA) with output power between 42.6 and 44.7 dBm, drain efficiency (DE) over 62%, and power additional efficiency (PAE) over 52% in the 2.3–3.5GHz frequency band. This PA effectively combines the high‐efficiency characteristics of class‐F PAs with the advantages of controlling the second harmonic for obtaining high efficiency at large bandwidth. The Dual Band Harmonic Control and Matching Network (DBHCN) realizes the conversion from 50 Ω to high‐efficiency impedance space (HEIS) while controlling the high‐order harmonics in different frequency bands. The proposed PA can be used for the fifth‐generation mobile communication technology (5G) base stations and broadband radars.

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Investigation of class-F power amplifier in the presence of the second and fourth harmonics of input voltage

Rostami,

Sheikhi

2024

Sci Rep

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In this paper, a thorough theoretical investigation of high-efficiency class-F power amplifier (PA) is undertaken to drive, considering the second and fourth harmonics of input voltage. The precise analytical expressions of the gate-source voltage, drain current, output power, and efficiency are extracted. Maximum normalized output power and maximum drain efficiency from the initial phase and amplitude of the second and fourth harmonics of input gate-voltage can be achieved. The simulation of class-F PA using a GaN CGH40010F transistor has been done to validate the theoretical analysis. Addition of the fourth harmonic gate voltage along with the second harmonic improves the output power and efficiency of the PA by 0.7 dBm and 4.1%. Based on the simulation with realistic elements, a highly efficient PA operating from 1.8 to 2.2 GHz is implemented. The fabricated PA provides an efficiency of 72–87.6%, PAE of 65–80% and an output power of 39.3–41 dBm.

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Design of a Class-F Power Amplifier with GaN Device Model and Reflection Data

Cited by 4 publications

References 15 publications

Design and Optimization of 2.1 mW ULP Doherty Power Amplifier with Interstage Capacitances Using 65 nm CMOS Technology

Design and Optimization of 2.1 mW ULP Doherty Power Amplifier with Interstage Capacitances Using 65 nm CMOS Technology

Design of a broadband power amplifier based on high‐efficiency impedance space

Investigation of class-F power amplifier in the presence of the second and fourth harmonics of input voltage

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