Design of a 14-bit Pipelined ADC using Ring Amplifier

Abstract

With the progress of integrated circuit technology, the intrinsic gain of transistors has become increasingly low, and the power consumption and complexity of OTA operational amplifiers have become higher, increasing the overall design difficulty of pipeline ADC. In order to improve the gain of the operational amplifier, improve the overall accuracy of the ADC, and reduce circuit power consumption, a 14-bit 20MSPS analog-to-digital converter with a pipeline structure of 2.5bit-2.5bit-2.5bit-2.5bit-2.5bit-2.5bit-2.5bit-2.5bit-2bit was designed using the SMIC 40nm process and analog drive digital technology under a 1.2V power supply voltage based on a new type of ring amplifier.The simulation results show that the SNDR of the input low-frequency signal pipeline ADC is 70.47dB, the SFDR is 85.5dB, and the ENOB is 11.45bit. When inputting high-frequency signals, the SNDR of the pipeline ADC is 68.35dB, the SFDR is 81.3dB, and the ENOB is 11.07bit.