Design of 8 bit and 16 bit Reversible ALU for Low Power Applications

Chandralekha, Vuppala; Navya, Latchapatula; Syamala, Neelam; Sanapala, Kishore

doi:10.1109/iccca49541.2020.9250876

Cited by 4 publications

(1 citation statement)

References 9 publications

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“…The ALU designs built using Vedic multiplier and Booth multiplier are compared by the Lachireddy and Ramesh, with Vedic multiplier having better performance in terms of area and power [7]. The author Chanfralekha et alhave designed and implemented 8 bit and 16-bit ALU to perform the operations of sum, not and nor [8]. The reversible gate decreases the use and loss of data bits and also improves the power utilization.…”

Section: Introductionmentioning

confidence: 99%

Design and Analysis of Multiplier Accumulator Circuit for DSP Applications

Frank¹,

Ramesh²

2022

International Journal of Advanced Science and Engineering

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Section: Introductionmentioning

confidence: 99%

Design and Analysis of Multiplier Accumulator Circuit for DSP Applications

Frank¹,

Ramesh²

2022

International Journal of Advanced Science and Engineering

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Comparative Review of MAC Architectures

Dinesh¹,

Sanapala²,

Jyothi

et al. 2021

Soft Computing for Intelligent Systems

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Performance Analysis of Multicore Processor Using FOFO-Based Approximate Compatible ALU

Senthilmurugan,

Gunaseelan

2023

J CIRCUIT SYST COMP

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Modern electronic devices are supported by multicore processors and they have become an unavoidable part of recent technologies. The Arithmetic Logic Unit (ALU) is one of the indispensable parts of the Central Processing Unit (CPU) which performs most of the operations. Operations like multiplications, and exponentials consume more power than other normal operations. Power management is one of the major challenges in designing processors. To maximize speed and reduce power consumption, a new technique in Multiplier and ALU incorporated with a multicore processor has been proposed. The Proposed Approximate Compatible ALU (ACALU) is designed to perform specified operations that consume more power, using an advanced multiplication technique called the First One First Operand (FOFO) method. The selection process of eight bits is done by the FOFO method followed by error detection and error approximation is performed to get the accurate output. The ACALU performs these operations in the Approximate Computing Mode which utilizes only eight bits for the operations, thus reducing the power consumption. The results of several analyses between multipliers, ALUs, and microprocessors are provided. As we optimize the multiplier and ALU unit, the multicore processor is also enhanced. The proposed multicore processor is compared with the AMD processor and the latest INTEL processor and the comparison results show that the proposed technique is 95.2% and 97.8% more efficient than the existing processors. Thus, the power consumption is minimized and the performance speed is increased in the proposed multicore processor.

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Design of 8 bit and 16 bit Reversible ALU for Low Power Applications

Cited by 4 publications

References 9 publications

Design and Analysis of Multiplier Accumulator Circuit for DSP Applications

Design and Analysis of Multiplier Accumulator Circuit for DSP Applications

Comparative Review of MAC Architectures

Performance Analysis of Multicore Processor Using FOFO-Based Approximate Compatible ALU

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