Design Obfuscation through Selective Post-Fabrication Transistor-Level Programming

Shihab, Mustafa M.; Tian, Jingxiang; Reddy, Gaurav Rajavendra; Hu, Bo; Swartz, William J.; Schaefer, Benjamin Carrion; Sechen, Carl; Makris, Yiorgos

doi:10.23919/date.2019.8714856

Cited by 21 publications

(3 citation statements)

References 13 publications

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“…A recent trend in obfuscation research is the use of embedded FPGA (eFPGA) [21], [22]. A very similar approach is also found in [23], where authors perform obfuscation with transistor-level granularity. While there are advantages to this practice, it has been used selectively to only protect key portions of a design and therefore keep the performance penalty as low as possible.…”

Section: Comparison and Discussionmentioning

confidence: 88%

From FPGAs to Obfuscated eASICs: Design and Security Trade-offs

Abideen¹,

Perez²,

Pagliarini³

2021

Preprint

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Threats associated with the untrusted fabrication of integrated circuits (ICs) are numerous: piracy, overproduction, reverse engineering, hardware trojans, etc. The use of reconfigurable elements (i.e., look-up tables as in FPGAs) is a known obfuscation technique. In the extreme case, when the circuit is entirely implemented as an FPGA, no information is revealed to the adversary but at a high cost in area, power, and performance. In the opposite extreme, when the same circuit is implemented as an ASIC, best-in-class performance is obtained but security is compromised. This paper investigates an intermediate solution between these two. Our results are supported by a custom CAD tool that explores this FPGA-ASIC design space and enables a standardcell based physical synthesis flow that is flexible and compatible with current design practices. Layouts are presented for obfuscated circuits in a 65nm commercial technology, demonstrating the attained obfuscation both graphically and quantitatively. Furthermore, our security analysis revealed that for truly hiding the circuit's intent (not only portions of its structure), the obfuscated design also has to chiefly resemble an FPGA: only some small amount of logic can be made static for an adversary to remain unaware of what the circuit does.

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Section: Comparison and Discussionmentioning

confidence: 88%

From FPGAs to Obfuscated eASICs: Design and Security Trade-offs

Abideen¹,

Perez²,

Pagliarini³

2021

Preprint

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“…Locking techniques can be applied at all steps of the IC design flow. Post-synthesis techniques work at transistor [27] and netlist level [33]. Pre-synthesis techniques work at RTL [18] or HLS level [20,34].…”

Section: Related Workmentioning

confidence: 99%

A Composable Design Space Exploration Framework to Optimize Behavioral Locking

Collini

Karri

Pilato

2022

2022 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

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Globalization of the integrated circuit (IC) supply chain exposes designs to security threats such as reverse engineering and intellectual property (IP) theft. Designers may want to protect specific high-level synthesis (HLS) optimizations or microarchitectural solutions of their designs. Hence, protecting the IP of ICs is essential. Behavioral locking is an approach to thwart these threats by operating at high levels of abstraction instead of reasoning on the circuit structure. Like any security protection, behavioral locking requires additional area. Existing locking techniques have a different impact on security and overhead, but they do not explore the effects of alternatives when making locking decisions. We develop a design-space exploration (DSE) framework to optimize behavioral locking for a given security metric. For instance, we optimize differential entropy under area or key-bit constraints. We define a set of heuristics to score each locking point by analyzing the system dependence graph of the design. The solution yields better results for 92% of the cases when compared to baseline, state-of-the-art (SOTA) techniques. The approach has results comparable to evolutionary DSE while requiring 100× to 400× less computational time.

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“…A potentially un-trusted foundry manufactures the design without the programming information for the fabric (e.g., the configuration bit-stream) which the designer withholds. Fabrics include embedded field programmable gate arrays (eFPGAs) [4], [6], coarse-grained reconfigurable architectures [12], and transistor fabrics [13].…”

Section: Introductionmentioning

confidence: 99%

Exploring eFPGA-based Redaction for IP Protection

Bhandari¹,

Moosa²,

Tan³

et al. 2021

Preprint

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Recently, eFPGA-based redaction has been proposed as a promising solution for hiding parts of a digital design from untrusted entities, where legitimate end-users can restore functionality by loading the withheld bitstream after fabrication. However, when deciding which parts of a design to redact, there are a number of practical issues that designers need to consider, including area and timing overheads, as well as security factors. Adapting an open-source FPGA fabric generation flow, we perform a case study to explore the trade-offs when redacting different modules of open-source intellectual property blocks (IPs) and explore how different parts of an eFPGA contribute to the security. We provide new insights into the feasibility and challenges of using eFPGA-based redaction as a security solution.

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Design Obfuscation through Selective Post-Fabrication Transistor-Level Programming

Cited by 21 publications

References 13 publications

From FPGAs to Obfuscated eASICs: Design and Security Trade-offs

From FPGAs to Obfuscated eASICs: Design and Security Trade-offs

A Composable Design Space Exploration Framework to Optimize Behavioral Locking

Exploring eFPGA-based Redaction for IP Protection

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