Design, modeling and characterization of on-chip transformer for silicon RFIC

Abstract

On-chip inductors play a crucial role in radio frequency integrated circuits (RFICs). For gigahertz circuitry, these components are usually realized using bond-wires or planar metal traces that route in the spiral or symmetrical configuration. In recent years, demand for multiple inductors in each RFIC application has driven the development of on-chip transformers. In fact, the physical isolation property of the transformers has already facilitated the integration of many large functional blocks (impedance matching, low-noise feedback, differential-to-single-ended conversion) into the silicon wafer. Furthermore, they permit a large range of inductances to be realized. However, these transformers possess a drawback of smaller quality-factor (Q) values with various loss mechanisms and are more difficult to model. In this dissertation, a scalable model has been developed for the proposed stackedtransformer lumped-element circuit. It is subsequently extended to a geometry-based scalable model that is suitable for performance optimization. A total number of 48 stacked transformers have been designed and fabricated for model development and verification. The scalable model is evaluated to have an error of < 7 % as compared to the silicon measurement results. Five challenges have been identified based on two mostcommonly used transformer designs, Interleaved and Stacked transformer designs. To circumvent these five challenges, 2 conceptual designs are developed and patented. They are the Symmetrical (Sym) & Fully Symmetrical Transformer (FST) designs and the High Effective Turn-ratio (HETR) design. The Sym and FST designs provide solutions to low electrical coupling limitation and asymmetricity nature of monolithic transformer designs. With the proposed patented interdigitization technique for the transformer windings, an identical inductors pair with higher individual coil self-resonant frequency (from f SRF (Stacked) = 7.5GHz to f SRF (Sym) = 9.3GHz) is achieved. On top of that, these 1 ATTENTION: The Singapore Copyright Act applies to the use of this document. Nanyang Technological University Library proposed designs can achieve > 50 % reduction in the silicon estate area, based on the comparison between the states-of-the-arts transformer designs with similar performance parameters. The symmetricity and performance enhancement are further silicon verified using a differential 2-stage PA circuit and a differential LNA design. Both the proposed designs are able to produce comparable gain with significant physical area reduction. The second patented design demonstrates the ability to achieve extremely high unit inductance value ever reported on silicon. The inductance ratio between the primary and secondary winding presented in this dissertation exceeds 30 with minimum area consumption. The proposed inductance synthesizer is able to yield < 3 % of matching error over a wide range of inductance value, based on the proposed equations. All the silicon data reported in this work are based on Chartered Semiconductor Manufact...