Design Methodology Based on the Inversion Coefficient and its Application to Inductorless LNA Implementations

Guitton, Gabrielle; Souza, Marcelo de; Mariano, André; Taris, Thierry

doi:10.1109/tcsi.2019.2914502

Cited by 16 publications

(22 citation statements)

References 20 publications

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“…The proposed LNA achieves the highest voltage gain in HP-mode with [16], and among the lowest power consumption (350uW) in LP-Mode with [8][9] [10]. We observe the limitation on the power consumption strongly impacts the noise figure, which remains above 4dB for a PDC below 600uW [8][9][10][11][12][13]. Interestingly, the noise figure limitation seems to be technology independent.…”

Section: Measurement Resultsmentioning

confidence: 99%

“…The MOS transistor described with the IC operates in WI when IC<0.1, in the Moderate Inversion (MI) when 0.1<IC<10, and in SI when IC>10. The small signal model of a MOS transistor, reported in Appendix [12], is used to exploit the analytic derivations (1), ( 2) and (3). To explore the design space of the circuit, the algorithm illustrated in Fig.…”

Section: A Ekv Model and Design Space Explorationmentioning

confidence: 99%

“…8) depends on the number of devices operating respectively in the MI region and the WI region. The model parameters are derived in Table III, expressions (6) to (12) accounting for m, the number of transistors operating in the WI region. Since ICMI >> ICWI, we can assume that the equivalent inversion coefficient ICeq (6), drain current IDeq (7), transconductance gmeq (8), and output conductance gdseq (9), are determined by the number of transistor operating in the MI region (N-m).…”

Section: Figure 7 Drain Current Of a 50um/28nm Fdsoi Nmos Transistor Versus Vgs As A Function Of Vbgmentioning

confidence: 99%

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Inductorless Multi-Mode RF-CMOS Low Noise Amplifier Dedicated to Ultra Low Power Applications

et al. 2021

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This work presents and analyses the design of a multi-mode Low Noise Amplifier (LNA) dedicated to 2.4GHz Wireless Sensor Network (WSN) applications. The proposed inductorless LNA, implemented in a 28nm FDSOI CMOS technology, is based on a common-gate configuration imbedded with a common-source stage to boost the overall transconductance of the circuit. The LNA is specifically designed, and optimized, to address three modes of operation. The reconfiguration is performed through current tuning, combined with switching the back gate of the amplification transistors. The proposed implementation allows the figure of merit (FOM) to be maintained constant in the different modes of operation. In the low power mode, the LNA only consumes 350uW. It achieves a voltage gain (Gv) of 16.8dB and a noise figure (NF) of 6.6dB. In the medium performance mode, the gain and the NF are respectively improved to 19.4dB and 5.4dB, the power consumption is 0.9mW. In the high-performance mode, the gain is maximum, 22.9dB, and the noise figure is minimum, 3.6dB, for a power consumption of 2mW. The linearity represented by the input referred third-order intercept point (IIP3) is constant, close to -16dBm. The reported LNA occupies only 0.0015mm 2 .

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Section: Measurement Resultsmentioning

confidence: 99%

Section: A Ekv Model and Design Space Explorationmentioning

confidence: 99%

Section: Figure 7 Drain Current Of a 50um/28nm Fdsoi Nmos Transistor Versus Vgs As A Function Of Vbgmentioning

confidence: 99%

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Inductorless Multi-Mode RF-CMOS Low Noise Amplifier Dedicated to Ultra Low Power Applications

et al. 2021

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“…Despite its low number of components, optimizing these kinds of LNA present some difficulties that diverse methodologies try to overcome by different strategies ranging from analytical expressions [11] to synthesis algorithms [12] or intermediate approaches [13].…”

Section: Introductionmentioning

confidence: 99%

“…The proposed methodology employs contour maps in a different approach than usual. While the typical use of these graphics implies representing the gradient of a single parameter versus two variables [13]- [15]; contour maps from this work sacrifice gradient data to specification limit from several parameters. This work is organized as follows.…”

Section: Introductionmentioning

confidence: 99%

Design-Window Methodology for Inductorless Noise-Cancelling CMOS LNAs

et al. 2022

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This paper presents an optimization methodology for inductorless noise-cancelling CMOS Low-Noise Amplifiers (LNA), whose performance typically depends on a tight balance in the design of two transistor stages. Due to the different functions of the two parts, noise-cancelling amplifiers become very difficult to analyze in detail by closed-form expressions or straight simulations: each section significantly affects the results of the other. In addition, opposed specifications, such as gain and cut-off frequency, suppose another grade of complexity due to the interplay of the two branches of the circuit. As a solution, the proposed methodology uses a visualization of the design window in 2-dimensional space to optimize the different parameters of the specifications without compromising the others. All specification constraints are represented in a single figure instead of one graph per parameter. Compared with most optimization methods, the design window methodology observes the design span instead of isolated design points that might not guarantee feasibility. Furthermore, as a simulation-driven exploration method, it benefits from complete device models with high-order effects that would be too complex to include in analytical expressions but critical to achieving maximum efficiency. As an example of the method, the paper describes the optimization of the well-known CS-CG noisecancelling LNA in 65-nm standard CMOS technology. Final post-layout simulations report very competitive results with a 3.7-dB noise figure, a 17-dB gain, and a cut-off frequency above 7 GHz.

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